Characterization of bitline stress effects on flash cell after program/erase cycle

Y. C. Liu*, Jyh-Chyurn Guo, K. L. Chang, C. I. Huang, M. T. Wang, A. Chang, F. Shone

*此作品的通信作者

研究成果: Conference article同行評審

1 引文 斯高帕斯(Scopus)

摘要

The impact of degradation of Flash memory cell characteristics caused by bitline stress during program/erase cycling is investigated considering the accentuated generation rate of negative oxide trap charges and interface-states. A special emphasis is focused on the observation of a significant amount of hole traps and their movement into the channel region. These oxide damages dramatically alter the device characteristics, and initiate severe read-disturb issue.

原文English
頁(從 - 到)97-103
頁數7
期刊Annual Proceedings - Reliability Physics (Symposium)
DOIs
出版狀態Published - 1 1月 1997
事件Proceedings of the 1997 35th Annual IEEE International Reliability Physics Symposium - Denver, CO, USA
持續時間: 8 4月 199710 4月 1997

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