Characteristics of gate-all-around twin poly-Si nanowire thin-film transistors

Jeng-Tzong Sheu; Po Chun Huang; Tzu Shiun Sheu; Chen Chia Chen; Lu An Chen

doi:10.1109/LED.2008.2009956

Characteristics of gate-all-around twin poly-Si nanowire thin-film transistors

Jeng-Tzong Sheu^*, Po Chun Huang, Tzu Shiun Sheu, Chen Chia Chen, Lu An Chen

^*此作品的通信作者

奈米科技碩博班

研究成果: Article › 同行評審

29 引文斯高帕斯（Scopus）

摘要

We have investigated the characteristics of gate-all-around (GAA) twin polycrystalline-silicon nanowire (NW) thin-film transistors (TFTs). The NW channel and surrounding gate imparted the GAA twin NW TFT with superior channel controllability. Moreover, the combination of the high surface-to-volume ratio of the NW and the split channel structure led to highly efficient NH₃ plasma treatment, which reduced the effective grain-boundary trap-state density. The GAA twin NW TFT exhibited greatly improved electrical performance, including a lower threshold voltage, a steeper subthreshold swing (114 mV/dec), a higher on/off current ratio (> 10⁸), and a virtual absence of drain-induced barrier lowering (13 mV/V).

原文	American English
頁（從 - 到）	139-141
頁數	3
期刊	IEEE Electron Device Letters
卷	30
發行號	2
DOIs	https://doi.org/10.1109/LED.2008.2009956
出版狀態	Published - 7 1月 2009

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10.1109/LED.2008.2009956

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title = "Characteristics of gate-all-around twin poly-Si nanowire thin-film transistors",

abstract = "We have investigated the characteristics of gate-all-around (GAA) twin polycrystalline-silicon nanowire (NW) thin-film transistors (TFTs). The NW channel and surrounding gate imparted the GAA twin NW TFT with superior channel controllability. Moreover, the combination of the high surface-to-volume ratio of the NW and the split channel structure led to highly efficient NH3 plasma treatment, which reduced the effective grain-boundary trap-state density. The GAA twin NW TFT exhibited greatly improved electrical performance, including a lower threshold voltage, a steeper subthreshold swing (114 mV/dec), a higher on/off current ratio (> 108), and a virtual absence of drain-induced barrier lowering (13 mV/V).",

keywords = "Gate-all-around (GAA), Nanowire (NW), Plasma treatment, Short-channel effects (SCEs), Thin-film transistor (TFT)",

author = "Jeng-Tzong Sheu and Huang, {Po Chun} and Sheu, {Tzu Shiun} and Chen, {Chen Chia} and Chen, {Lu An}",

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AU - Sheu, Jeng-Tzong

AU - Huang, Po Chun

AU - Sheu, Tzu Shiun

AU - Chen, Chen Chia

AU - Chen, Lu An

PY - 2009/1/7

Y1 - 2009/1/7

N2 - We have investigated the characteristics of gate-all-around (GAA) twin polycrystalline-silicon nanowire (NW) thin-film transistors (TFTs). The NW channel and surrounding gate imparted the GAA twin NW TFT with superior channel controllability. Moreover, the combination of the high surface-to-volume ratio of the NW and the split channel structure led to highly efficient NH3 plasma treatment, which reduced the effective grain-boundary trap-state density. The GAA twin NW TFT exhibited greatly improved electrical performance, including a lower threshold voltage, a steeper subthreshold swing (114 mV/dec), a higher on/off current ratio (> 108), and a virtual absence of drain-induced barrier lowering (13 mV/V).

AB - We have investigated the characteristics of gate-all-around (GAA) twin polycrystalline-silicon nanowire (NW) thin-film transistors (TFTs). The NW channel and surrounding gate imparted the GAA twin NW TFT with superior channel controllability. Moreover, the combination of the high surface-to-volume ratio of the NW and the split channel structure led to highly efficient NH3 plasma treatment, which reduced the effective grain-boundary trap-state density. The GAA twin NW TFT exhibited greatly improved electrical performance, including a lower threshold voltage, a steeper subthreshold swing (114 mV/dec), a higher on/off current ratio (> 108), and a virtual absence of drain-induced barrier lowering (13 mV/V).

KW - Gate-all-around (GAA)

KW - Nanowire (NW)

KW - Plasma treatment

KW - Short-channel effects (SCEs)

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JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

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Characteristics of gate-all-around twin poly-Si nanowire thin-film transistors

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