Characteristics of gate-all-around junctionless polysilicon nanowire transistors with twin 20-nm gates

Tung Yu Liu; Fu-Ming Pan; Jeng-Tzong Sheu

doi:10.1109/JEDS.2015.2441736

Characteristics of gate-all-around junctionless polysilicon nanowire transistors with twin 20-nm gates

Tung Yu Liu, Fu-Ming Pan, Jeng-Tzong Sheu^*

^*此作品的通信作者

研究成果: Article › 同行評審

29 引文斯高帕斯（Scopus）

摘要

A high performance gate-all-around (GAA) junctionless (JL) polycrystalline silicon nanowire (poly-Si NW) transistor with channel width of 12 nm, channel thickness of 45 nm, and gate length of 20 nm has been successfully demonstrated, based on a simplified double sidewall spacer process. Without suffering serious short-channel effects, the GAA JL poly-Si NW device exhibits excellent electrical characteristics, including a subthreshold swing of 105 mV/dec, a drain-induced barrier lowering of 83 mV/V, and a high I_on I_off current ratio of 7 × 10^-8 (V_G = 4 V and V_D = 1 V). Such GAA JL poly-Si NW devices exhibit potential for low-power electronics and future 3-D IC applications.

原文	English
文章編號	7118129
頁（從 - 到）	405-409
頁數	5
期刊	IEEE Journal of the Electron Devices Society
卷	3
發行號	5
DOIs	https://doi.org/10.1109/JEDS.2015.2441736
出版狀態	Published - 1 9月 2015

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10.1109/JEDS.2015.2441736

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title = "Characteristics of gate-all-around junctionless polysilicon nanowire transistors with twin 20-nm gates",

abstract = "A high performance gate-all-around (GAA) junctionless (JL) polycrystalline silicon nanowire (poly-Si NW) transistor with channel width of 12 nm, channel thickness of 45 nm, and gate length of 20 nm has been successfully demonstrated, based on a simplified double sidewall spacer process. Without suffering serious short-channel effects, the GAA JL poly-Si NW device exhibits excellent electrical characteristics, including a subthreshold swing of 105 mV/dec, a drain-induced barrier lowering of 83 mV/V, and a high Ion Ioff current ratio of 7 × 10-8 (VG = 4 V and VD = 1 V). Such GAA JL poly-Si NW devices exhibit potential for low-power electronics and future 3-D IC applications.",

keywords = "Gate-all-around (GAA), junctionless (JL), nanowire (NW), poly-Si, sidewall spacer, transistor",

author = "Liu, {Tung Yu} and Fu-Ming Pan and Jeng-Tzong Sheu",

note = "Publisher Copyright: {\textcopyright} 2013 IEEE.",

year = "2015",

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doi = "10.1109/JEDS.2015.2441736",

language = "English",

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T1 - Characteristics of gate-all-around junctionless polysilicon nanowire transistors with twin 20-nm gates

AU - Liu, Tung Yu

AU - Pan, Fu-Ming

AU - Sheu, Jeng-Tzong

PY - 2015/9/1

Y1 - 2015/9/1

N2 - A high performance gate-all-around (GAA) junctionless (JL) polycrystalline silicon nanowire (poly-Si NW) transistor with channel width of 12 nm, channel thickness of 45 nm, and gate length of 20 nm has been successfully demonstrated, based on a simplified double sidewall spacer process. Without suffering serious short-channel effects, the GAA JL poly-Si NW device exhibits excellent electrical characteristics, including a subthreshold swing of 105 mV/dec, a drain-induced barrier lowering of 83 mV/V, and a high Ion Ioff current ratio of 7 × 10-8 (VG = 4 V and VD = 1 V). Such GAA JL poly-Si NW devices exhibit potential for low-power electronics and future 3-D IC applications.

AB - A high performance gate-all-around (GAA) junctionless (JL) polycrystalline silicon nanowire (poly-Si NW) transistor with channel width of 12 nm, channel thickness of 45 nm, and gate length of 20 nm has been successfully demonstrated, based on a simplified double sidewall spacer process. Without suffering serious short-channel effects, the GAA JL poly-Si NW device exhibits excellent electrical characteristics, including a subthreshold swing of 105 mV/dec, a drain-induced barrier lowering of 83 mV/V, and a high Ion Ioff current ratio of 7 × 10-8 (VG = 4 V and VD = 1 V). Such GAA JL poly-Si NW devices exhibit potential for low-power electronics and future 3-D IC applications.

KW - Gate-all-around (GAA)

KW - junctionless (JL)

KW - nanowire (NW)

KW - poly-Si

KW - sidewall spacer

KW - transistor

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JO - IEEE Journal of the Electron Devices Society

JF - IEEE Journal of the Electron Devices Society

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Characteristics of gate-all-around junctionless polysilicon nanowire transistors with twin 20-nm gates

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