Characteristics of Dual-gated Poly-Si Junctionless Nanowire Transistors with Asymmetrical Source/drain Offsets

You Tai Chang, Ruei Jen Wu, Kang Ping Peng, Chun Jung Su, Pei-Wen Li, Horng-Chih Lin*

*此作品的通信作者

    研究成果: Conference contribution同行評審

    摘要

    In this paper, a novel gate-all-around (GAA) junctionless (JL) nanowire (NW) transistor with dual gate was proposed, fabricated and characterized. The fabricated transistors exhibit well-behaved performance with on/off current ratio of ~106 and subthreshold swing of 76 mV/decade. An important finding of notes is that when drain bias is applied to the end of the NW with a longer channel offset, the drain current is lower than that applied to the shorter end.

    原文English
    主出版物標題2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020
    發行者Institute of Electrical and Electronics Engineers Inc.
    頁面57-58
    頁數2
    ISBN(電子)9781728197357
    ISBN(列印)978-1-7281-9736-4
    DOIs
    出版狀態Published - 六月 2020
    事件2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020 - Honolulu, United States
    持續時間: 13 六月 202014 六月 2020

    出版系列

    名字2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020

    Conference

    Conference2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020
    國家/地區United States
    城市Honolulu
    期間13/06/2014/06/20

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