Categorization of Multilevel-Cell Storage-Class Memory: An RRAM Example

Jen Chieh Liu, Chung Wei Hsu, I. Ting Wang, Tuo-Hung Hou*

*此作品的通信作者

    研究成果: Article同行評審

    11 引文 斯高帕斯(Scopus)

    摘要

    This paper provides new insights into the effect of device characteristics on multilevel-cell (MLC) operation, aiming at potential benefits, such as the reduction of write latency and peripheral circuit design overhead. A general categorization of the MLC-operating schemes in storage-class memory (SCM) is proposed to connect the total number of write inputs with fundamental device properties. The categorization method is validated using two resistive random access memory devices based on different switching mechanisms. Favorable device characteristics and the corresponding simplified MLC operating schemes are addressed to facilitate future development of MLC SCM.

    原文English
    文章編號7140778
    頁(從 - 到)2510-2516
    頁數7
    期刊IEEE Transactions on Electron Devices
    62
    發行號8
    DOIs
    出版狀態Published - 1 8月 2015

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