Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC

Ming-Dou Ker*, Chung-Yu Wu, Tao Cheng, Hun Hsien Chang

*此作品的通信作者

研究成果: Article同行評審

52 引文 斯高帕斯(Scopus)

摘要

Capacitor-couple technique used to lower snapback-trigger voltage and to ensure uniform ESD current distribution in deep-submicron CMOS on-chip ESD protection circuit is proposed. The coupling capacitor is realized by a poly layer right under the wire-bonding metal pad without increasing extra layout area to the pad. A timing-original design model has been derived to calculate the capacitor-couple efficiency of this proposed ESD protection circuit. Using this capacitor-couple ESD protection circuit, the thinner gate oxide of CMOS devices in deep-submicron low-voltage CMOS ASIC can be effectively protected.

原文English
頁(從 - 到)307-321
頁數15
期刊IEEE Transactions on Very Large Scale Integration (VLSI) Systems
4
發行號3
DOIs
出版狀態Published - 1996

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