Cache Capacity Aware Thread Scheduling for Irregular Memory Access on many-core GPGPUs

Hsien Kai Kuo, Ta Kan Yen, Bo-Cheng Lai, Jing Yang Jou

    研究成果: Conference contribution同行評審

    11 引文 斯高帕斯(Scopus)

    摘要

    On-chip shared cache is effective to alleviate the memory bottleneck in modern many-core systems, such as GPGPUs. However, when scheduling numerous concurrent threads on a GPGPU, a cache capacity agnostic scheduling scheme could lead to severe cache contention among threads and thus significant performance degradation. Moreover, the diverse working sets in irregular applications make the cache contention issue an even more serious problem. As a result, taking cache capacity into account has become a critical scheduling issue of GPGPUs. This paper formulates a Cache Capacity Aware Thread Scheduling Problem to capture the impact of cache capacity as well as different architectural considerations. With a proof to be NP-hard, this paper has proposed two algorithms to perform the cache capacity aware thread scheduling. The simulation results on Nvidia's Fermi configuration have shown that the proposed scheduling scheme can effectively avoid cache contention, and achieve an average of 44.7% cache miss reduction and 28.5% runtime enhancement. The paper also shows the runtime can be enhanced up to 62.5% for more complex applications.

    原文English
    主出版物標題2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013
    頁面338-343
    頁數6
    DOIs
    出版狀態Published - 20 5月 2013
    事件2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013 - Yokohama, Japan
    持續時間: 22 1月 201325 1月 2013

    出版系列

    名字Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

    Conference

    Conference2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013
    國家/地區Japan
    城市Yokohama
    期間22/01/1325/01/13

    指紋

    深入研究「Cache Capacity Aware Thread Scheduling for Irregular Memory Access on many-core GPGPUs」主題。共同形成了獨特的指紋。

    引用此