BTI-aware sleep transistor sizing algorithm for reliable power gating designs

Kai-Chiang Wu*, Ing Chao Lin, Yao Te Wang, Shuen Shiang Yang

*此作品的通信作者

研究成果: Article同行評審

9 引文 斯高帕斯(Scopus)

摘要

Power gating is an effective way to reduce leakage power. This technique uses high Vth transistors, called sleep transistors, to turn off the power supply. However, sleep transistors suffer from the bias temperature instability (BTI) effect, resulting in an increased Vth, and reduced reliability. This paper proposes two BTI-aware sleep transistor sizing algorithms to reduce the total width of sleep transistors based on the distributed sleep transistor network structure. The proposed algorithms reduce total width by more than 16.08%. More area can be reduced if the BTI effect on both sleep and cluster transistors is considered.

原文English
文章編號6899800
頁(從 - 到)1591-1595
頁數5
期刊IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
33
發行號10
DOIs
出版狀態Published - 1 十月 2014

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