@inproceedings{909942789dce41fe8a80f1f479ecf167,
title = "BSRA: Block-based Super Resolution Accelerator with Hardware Efficient Pixel Attention",
abstract = "Increasingly, convolution neural network (CNN) based super resolution models have been proposed for better reconstruction results, but their large model size and complicated structure inhibit their real-time hardware implementation. Current hardware designs are limited to a plain network and suffer from lower quality and high memory bandwidth requirements. This paper proposes a super resolution hardware accelerator with hardware efficient pixel attention that just needs 25. 9K parameters and simple structure but achieves 0. 38dB better reconstruction images than the widely used FSRCNN. The accelerator adopts full model block wise convolution for full model layer fusion to reduce external memory access to model input and output only. In addition, CNN and pixel attention are well supported by PE arrays with distributed weights. The final implementation can support full HD image reconstruction at 30 frames per second with TSMC 40nm CMOS process.",
keywords = "Convolution neural network, deep learning accelerators, pixel attention mechanism, super resolution",
author = "Yang, {Dun Hao} and Chang, {Tian Sheuan}",
note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022 ; Conference date: 27-05-2022 Through 01-06-2022",
year = "2022",
doi = "10.1109/ISCAS48785.2022.9937462",
language = "English",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "2821--2825",
booktitle = "IEEE International Symposium on Circuits and Systems, ISCAS 2022",
address = "美國",
}