BSRA: Block-based Super Resolution Accelerator with Hardware Efficient Pixel Attention

Dun Hao Yang, Tian Sheuan Chang

研究成果: Conference contribution同行評審

6 引文 斯高帕斯(Scopus)

摘要

Increasingly, convolution neural network (CNN) based super resolution models have been proposed for better reconstruction results, but their large model size and complicated structure inhibit their real-time hardware implementation. Current hardware designs are limited to a plain network and suffer from lower quality and high memory bandwidth requirements. This paper proposes a super resolution hardware accelerator with hardware efficient pixel attention that just needs 25. 9K parameters and simple structure but achieves 0. 38dB better reconstruction images than the widely used FSRCNN. The accelerator adopts full model block wise convolution for full model layer fusion to reduce external memory access to model input and output only. In addition, CNN and pixel attention are well supported by PE arrays with distributed weights. The final implementation can support full HD image reconstruction at 30 frames per second with TSMC 40nm CMOS process.

原文English
主出版物標題IEEE International Symposium on Circuits and Systems, ISCAS 2022
發行者Institute of Electrical and Electronics Engineers Inc.
頁面2821-2825
頁數5
ISBN(電子)9781665484855
DOIs
出版狀態Published - 2022
事件2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022 - Austin, 美國
持續時間: 27 5月 20221 6月 2022

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
2022-May
ISSN(列印)0271-4310

Conference

Conference2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022
國家/地區美國
城市Austin
期間27/05/221/06/22

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