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BSIM-BULK: Accurate Compact Model for Analog and RF Circuit Design

  • Chetan Gupta
  • , Ravi Goel
  • , Harshit Agarwal
  • , Chen-Ming Hu
  • , Yogesh Singh Chauhan

研究成果: Conference contribution同行評審

15 引文 斯高帕斯(Scopus)

摘要

In this work, we present the recent and upcoming enhancements of the industry standard BSIM-BULK (formerly BSIM6) model. BSIM-BULK is the latest body referenced compact model for bulk MOSFETs having a unified core, which is developed by the BSIM group for accurate design of analog and RF circuits. The model satisfies the symmetry test for DC and AC, correctly predicts harmonic slope, and exhibits accurate results for RF and analog simulations. In order to further improve the model accuracy for transconductance (gm) and output conductance (gds), an analytical model for bulk charge effect, in both current and capacitance, is implemented. Several other advanced models are added to capture real device physics. These include: parasitic current at the shallow trench isolation edges; leakage current components in zero threshold voltage native devices; new model for NQS to capture the NQS effects up to the millimeter wave regime; self heating effect; and heavily halo implanted MOSFET's anomalous gm, flicker noise and IDS mismatch. All these enhancements have been implemented to high standards of computational efficiency and robustness.

原文English
主出版物標題2019 IEEE Custom Integrated Circuits Conference, CICC 2019
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781538693957
DOIs
出版狀態Published - 1 4月 2019
事件40th Annual IEEE Custom Integrated Circuits Conference, CICC 2019 - Austin, 美國
持續時間: 14 4月 201917 4月 2019

出版系列

名字Proceedings of the Custom Integrated Circuits Conference
2019-April
ISSN(列印)0886-5930

Conference

Conference40th Annual IEEE Custom Integrated Circuits Conference, CICC 2019
國家/地區美國
城市Austin
期間14/04/1917/04/19

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