BRAM efficient multi-ported memory on FPGA

Jiun Liang Lin, Bo-Cheng Lai

    研究成果: Conference contribution同行評審

    8 引文 斯高帕斯(Scopus)

    摘要

    Multi-ported memory is broadly used in modern designs on FPGAs. However, the excessive demand on BRAMs to implement multi-ported memory on FPGA would block the usage of BRAMs for other parts of a design. This issue becomes a serious concern especially for designs that require huge internal storage capacity. This paper proposes a BRAM efficient scheme on increasing read ports and write ports. When compared with previous works, the proposed multi-ported memory can reduce up to 53% requirement on BRAMs with only minor frequency degradation.

    原文English
    主出版物標題2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
    發行者Institute of Electrical and Electronics Engineers Inc.
    ISBN(電子)9781479962754
    DOIs
    出版狀態Published - 28 5月 2015
    事件2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 - Hsinchu, Taiwan
    持續時間: 27 4月 201529 4月 2015

    出版系列

    名字2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015

    Conference

    Conference2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
    國家/地區Taiwan
    城市Hsinchu
    期間27/04/1529/04/15

    指紋

    深入研究「BRAM efficient multi-ported memory on FPGA」主題。共同形成了獨特的指紋。

    引用此