Boron Ion Implantation-Induced Embedded Layers for Ultra-Thin Die Structures

More layers can be stacked in a three-dimensional integrated circuit (3D-IC) structure in the next generation of semiconductors. While stacking multiple layers, it is important to thin down every single layer to reduce the overall package size. Accurate selection of the backside etching stop layer can effectively help reduce the overall thickness of the 3D-IC structure and the silicon die thickness. In this study, a novel approach of different ion implantation-induced embedded layers as backside etching stop layers for ultra-thin die structures is presented. Boron ion implantation is used in silicon wafers, followed by a rapid thermal annealing (RTA) process and wet etch testing to determine the stable and higher etch selectivity. The results show that the final average etching rates of bare silicon and the boron-doped layers in the KOH solution are 22.4 nm/s and 1.8 nm/s, respectively, with the etch selectivity of about 12.4.