@inproceedings{89d1a998b49a47b6a2df49ca0d83ed32,
title = "Boosting the Performance of 3D Charge Trap NAND Flash with Asymmetric Feature Process Size Characteristic",
abstract = "The growing demands of large capacity fash-based storages have facilitated the down-scaling process of NAND fash memory. Among NAND fash technologies, 3D charge trap fash is regarded as one of the most promising candidates. Owing to the cylindrical geometry of vertical channels, the access performance of each page in one block is distinctive, and this situation is exaggerated in the 3D charge trap fash with the fast-growing number of layers. In this study, a progressive performance boosting strategy is proposed to boost the performance of 3D charge trap fash by utilizing its asymmetric page access speed feature. A series of experiments was conducted to demonstrate the capability of the proposed strategy on improving access performance of 3D charge trap flash.",
keywords = "3D NAND flash, flash storage, hot/cold identification",
author = "Chen, {Shuo Han} and Chen, {Yen Ting} and Wei, {Hsin Wen} and Shih, {Wei Kuan}",
note = "Publisher Copyright: {\textcopyright} 2017 ACM.; 54th Annual Design Automation Conference, DAC 2017 ; Conference date: 18-06-2017 Through 22-06-2017",
year = "2017",
month = jun,
day = "18",
doi = "10.1145/3061639.3062209",
language = "English",
series = "Proceedings - Design Automation Conference",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "Proceedings of the 54th Annual Design Automation Conference 2017, DAC 2017",
address = "美國",
}