A method utilizing Charged Device Model (CDM) discharging to emulate real-world Charged Board Model (CBM) discharging was proposed and successfully addressed the weakest spot of whole chip. In order to extract the correlation between CDM pre-fail voltage VCDM and CBM pre-fail voltage V CBM, the capacitance and discharging waveforms of output pin on an IC and Printed Circuit Board (PCB) were measured. The results showed that the CBM evaluation board (EB) was not a must for large-size chip, as LCD driver ICs. CDM discharging can be used to direct investigate the weak point of design/layout for large-size chip. Besides, this paper addresses the guidelines about chip-level ESD cell design and layout optimization against CBM ESD damage.