Bipolar Dual-LFSR Reseeding for Low-Power Testing

Jen Cheng Ying, Wang Dauh Tseng, W. J. Tsai

研究成果: Conference contribution同行評審

3 引文 斯高帕斯(Scopus)

摘要

Large test data volume and excessive test power are two strict challenges for VLSI circuit testing. Built-in self-Test (BIST) is recognized as a good solution to the problem of large test data volume. LFSR-decompressor-based compression methods have been widely adopted in BIST to reduce test data volume. The effectiveness of this approach is on the ability to control the generated pseudorandom pattern. This paper adopts dual-LFSR to effectively reduce the amount of test data while keeping the scan-in power as low. Experimental results show that it has a significant reduction of data volume and test power using the proposed new Bipolar Dual-LFSR reseeding approach as compared to the existing related dual-LFSR schemes.

原文English
主出版物標題DSC 2018 - 2018 IEEE Conference on Dependable and Secure Computing
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781538657904
DOIs
出版狀態Published - 23 1月 2019
事件2018 IEEE Conference on Dependable and Secure Computing, DSC 2018 - Kaohsiung, Taiwan
持續時間: 10 12月 201813 12月 2018

出版系列

名字DSC 2018 - 2018 IEEE Conference on Dependable and Secure Computing

Conference

Conference2018 IEEE Conference on Dependable and Secure Computing, DSC 2018
國家/地區Taiwan
城市Kaohsiung
期間10/12/1813/12/18

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