TY - JOUR
T1 - Avalanche ruggedness capability and improvement of 5-v n-channel large-array mosfet in bcd process
AU - Nidhi, Karuna
AU - Ker, Ming-Dou
AU - Lee, Jian Hsing
AU - Huang, Shao Chang
PY - 2019/7/1
Y1 - 2019/7/1
N2 - Energy handling capability of large-array devices (LADs) is one of the most dominating concerns for the designers that affect the device design and its reliability. In this paper, the improvement of the avalanche ruggedness capability by using an optional implantation layer has been investigated the first time for the application of 5-V n-channel large-array MOSFET in a bipolar-CMOS-DMOS (BCD) process. Experimental results with extensive measurements verified that the maximum avalanche current (IAV) achieved from the modified device is enhanced by more than twice. Moreover, the energy in avalanche single pulse (EAS) capability is improved by more than five times. A significant improvement is noticed in the avalanche safe-operating-area (A-SOA) as compared to the original device, and the failure analysis is discussed in detail. In addition, the impact of an optional implantation layer on the total gate charge (Qg) is also compared for a LAD with a total width of 12μm.
AB - Energy handling capability of large-array devices (LADs) is one of the most dominating concerns for the designers that affect the device design and its reliability. In this paper, the improvement of the avalanche ruggedness capability by using an optional implantation layer has been investigated the first time for the application of 5-V n-channel large-array MOSFET in a bipolar-CMOS-DMOS (BCD) process. Experimental results with extensive measurements verified that the maximum avalanche current (IAV) achieved from the modified device is enhanced by more than twice. Moreover, the energy in avalanche single pulse (EAS) capability is improved by more than five times. A significant improvement is noticed in the avalanche safe-operating-area (A-SOA) as compared to the original device, and the failure analysis is discussed in detail. In addition, the impact of an optional implantation layer on the total gate charge (Qg) is also compared for a LAD with a total width of 12μm.
KW - Avalanche ruggedness
KW - Avalanche safe-operating-area (A-SOA)
KW - Current in avalanche (IAV)
KW - Large-array device (LAD)
KW - Time in avalanche (tAV)
KW - Total gate charge (Qg)
KW - Unclamped inductive switching (UIS)
UR - http://www.scopus.com/inward/record.url?scp=85067677490&partnerID=8YFLogxK
U2 - 10.1109/TED.2019.2916032
DO - 10.1109/TED.2019.2916032
M3 - Article
AN - SCOPUS:85067677490
SN - 0018-9383
VL - 66
SP - 3040
EP - 3048
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
IS - 7
M1 - 8723307
ER -