TY - GEN
T1 - Automatic synthesis flow for voltage rectifiers with impedance consideration
AU - Jhou, Fang Yu
AU - Wang, Chang Han
AU - Wu, Tsung Yueh
AU - Lou, Yu Kang
AU - Liu, Chien-Nan
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/5/31
Y1 - 2016/5/31
N2 - For radio-frequency (RF) circuits, energy harvesting is one of the research topics in recent years. By converting ambient energy into the required electrical energy, the circuit can still perform its functionality without any extra power source. In RF energy harvesting circuits, the most important part is the rectifier circuit. Therefore, this paper proposes an automated design tool for CMOS multi-stage Dickson rectifiers to generate the required designs from specifications to layout with power and impedance considerations. In this paper, impedance matching has been taken into consideration to have a proper tradeoff between area and performance. Therefore, it can solve the difficulty in previous approaches to match the impedance after design. The proposed automation tool is consisted of two parts, circuit sizing and IC layout, which have been implemented in LINUX already. The generated Tcl layout scripts have been tested in commercial EDA tools and generated the corresponding layout successfully. As demonstrated in the experimental results, this tool is able to generate the required circuits and layouts that satisfy all users' specifications in seconds. It can help users to shorten the complicated RF IC design flow.
AB - For radio-frequency (RF) circuits, energy harvesting is one of the research topics in recent years. By converting ambient energy into the required electrical energy, the circuit can still perform its functionality without any extra power source. In RF energy harvesting circuits, the most important part is the rectifier circuit. Therefore, this paper proposes an automated design tool for CMOS multi-stage Dickson rectifiers to generate the required designs from specifications to layout with power and impedance considerations. In this paper, impedance matching has been taken into consideration to have a proper tradeoff between area and performance. Therefore, it can solve the difficulty in previous approaches to match the impedance after design. The proposed automation tool is consisted of two parts, circuit sizing and IC layout, which have been implemented in LINUX already. The generated Tcl layout scripts have been tested in commercial EDA tools and generated the corresponding layout successfully. As demonstrated in the experimental results, this tool is able to generate the required circuits and layouts that satisfy all users' specifications in seconds. It can help users to shorten the complicated RF IC design flow.
UR - http://www.scopus.com/inward/record.url?scp=84978429644&partnerID=8YFLogxK
U2 - 10.1109/VLSI-DAT.2016.7482536
DO - 10.1109/VLSI-DAT.2016.7482536
M3 - Conference contribution
AN - SCOPUS:84978429644
T3 - 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
BT - 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
Y2 - 25 April 2016 through 27 April 2016
ER -