Automatic common-centroid layout generation for binary-weighted capacitors in charge-scaling DAC

Wei Hao Hsiao*, Yi Ting He, Po-Hung Lin, Rong Guey Chang, Shuenn Yuh Lee

*此作品的通信作者

研究成果: Conference contribution同行評審

7 引文 斯高帕斯(Scopus)

摘要

As the precision of the capacitance ratios among binary-weighted capacitors is the key to accuracy/performance of charge-scaling digital-to-analog converters, it is very important to generate a highly matched common-centroid layout with minimum routing-induced parasitics. However, most of the previous works only focused on common-centroid placement optimization with the consideration of random and systematic mismatch. This paper introduces a novel common-centroid capacitor layout generation approach to minimize the parasitic impact on circuit accuracy/performance. Experimental results show that, compared with the manual layout, the layout generated by the presented approach can achieve even smaller layout area and better circuit accuracy/performance within much shorter time.

原文English
主出版物標題2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012
頁面173-176
頁數4
DOIs
出版狀態Published - 11 十二月 2012
事件2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012 - Seville, Spain
持續時間: 19 九月 201221 九月 2012

出版系列

名字2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012

Conference

Conference2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012
國家/地區Spain
城市Seville
期間19/09/1221/09/12

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