TY - GEN
T1 - Asymmetrical write-assist for single-ended SRAM operation
AU - Lin, Jihi Yu
AU - Tu, Ming Hsien
AU - Tsai, Ming Chien
AU - Jou, Shyh-Jye
AU - Chuang, Ching Te
PY - 2009
Y1 - 2009
N2 - In this paper, asymmetrical Write-assist cell virtual ground biasing and positive feedback sensing keeper schemes are proposed to improve the Read Static Noise Margin (RSNM), Write Margin (WM), and operation speed of a singleended Read/Write 8T SRAM cell. A 4Kbit SRAM implemented in 90nm CMOS technology achieves 1uW/bit average power consumption at 6MHz, Vmin of 410mV at 6MHz, and 234MHz maximum operation frequency at 600mV.
AB - In this paper, asymmetrical Write-assist cell virtual ground biasing and positive feedback sensing keeper schemes are proposed to improve the Read Static Noise Margin (RSNM), Write Margin (WM), and operation speed of a singleended Read/Write 8T SRAM cell. A 4Kbit SRAM implemented in 90nm CMOS technology achieves 1uW/bit average power consumption at 6MHz, Vmin of 410mV at 6MHz, and 234MHz maximum operation frequency at 600mV.
UR - http://www.scopus.com/inward/record.url?scp=77949609975&partnerID=8YFLogxK
U2 - 10.1109/SOCCON.2009.5398086
DO - 10.1109/SOCCON.2009.5398086
M3 - Conference contribution
AN - SCOPUS:77949609975
SN - 9781424452200
T3 - Proceedings - IEEE International SOC Conference, SOCC 2009
SP - 101
EP - 104
BT - Proceedings - IEEE International SOC Conference, SOCC 2009
T2 - IEEE International SOC Conference, SOCC 2009
Y2 - 9 September 2009 through 11 September 2009
ER -