Asymmetrical write-assist for single-ended SRAM operation

Jihi Yu Lin*, Ming Hsien Tu, Ming Chien Tsai, Shyh-Jye Jou, Ching Te Chuang

*此作品的通信作者

    研究成果: Conference contribution同行評審

    6 引文 斯高帕斯(Scopus)

    摘要

    In this paper, asymmetrical Write-assist cell virtual ground biasing and positive feedback sensing keeper schemes are proposed to improve the Read Static Noise Margin (RSNM), Write Margin (WM), and operation speed of a singleended Read/Write 8T SRAM cell. A 4Kbit SRAM implemented in 90nm CMOS technology achieves 1uW/bit average power consumption at 6MHz, Vmin of 410mV at 6MHz, and 234MHz maximum operation frequency at 600mV.

    原文English
    主出版物標題Proceedings - IEEE International SOC Conference, SOCC 2009
    頁面101-104
    頁數4
    DOIs
    出版狀態Published - 2009
    事件IEEE International SOC Conference, SOCC 2009 - Belfast, Ireland
    持續時間: 9 9月 200911 9月 2009

    出版系列

    名字Proceedings - IEEE International SOC Conference, SOCC 2009

    Conference

    ConferenceIEEE International SOC Conference, SOCC 2009
    國家/地區Ireland
    城市Belfast
    期間9/09/0911/09/09

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