Asymmetric electric field enhancement in nanocrystal memories

Chungho Lee*, Udayan Ganguly, Venkat Narayanan, Tuo-Hung Hou, Jinsook Kim, Edwin C. Kan

*此作品的通信作者

研究成果: Article同行評審

38 引文 斯高帕斯(Scopus)

摘要

The electrostatic model for nanocrystal memories is used to illustrate the fundamental difference of the metal nanocrystal memory in low-voltage program/erase (P/E) operations in comparison with semiconductor nanocrystal and trap-based memories. Due to repulsion of potential contours inside conductors, the metal nanocrystals will significantly enhance the electric field between the nanocrystal and the sensing channel set up by the control gate bias and, hence, can achieve much higher efficiency in low-voltage P/E. On the other hand, the electric field originated from the stored charge will only be slightly different for metal and semiconductor nanocrystal cases. We presented the electrostatic models by both approximate analytical formulation and three-dimensional numerical simulation in a nanocrystal array. Operations of P/E and read disturbance were analyzed for the cases of homogeneous charge distribution, silicon, and metal nanocrystals. In the P/E condition of +5/-5 V, the metal nanocrystal memory offers around 1.6 times higher peak fields than Si counterparts and almost three times higher than that from the one-dimensional model for homogeneous charge distribution. The field enhancement factor suggests the design criteria of oxide thickness, nanocrystal size, and spacing. The advantage of asymmetric field enhancement of metal nanocrystals will be even more prominent when high-K gate dielectrics are employed.

原文English
頁(從 - 到)879-881
頁數3
期刊Ieee Electron Device Letters
26
發行號12
DOIs
出版狀態Published - 12月 2005

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