跳至主導覽
跳至搜尋
跳過主要內容
國立陽明交通大學研發優勢分析平台 首頁
English
中文
首頁
人員
單位
研究成果
計畫
獎項
活動
貴重儀器
影響
按專業知識、姓名或所屬機構搜尋
Area minimization synthesis for reconfigurable single-electron transistor arrays with fabrication constraints
Yi Hang Chen
*
, Jian Yu Chen,
Juinn-Dar Huang
*
此作品的通信作者
研究成果
:
Conference contribution
›
同行評審
10
引文 斯高帕斯(Scopus)
總覽
指紋
指紋
深入研究「Area minimization synthesis for reconfigurable single-electron transistor arrays with fabrication constraints」主題。共同形成了獨特的指紋。
排序方式
重量
按字母排序
Keyphrases
Reconfigurable
100%
Area Minimization
100%
Single Electron Transistor
100%
Transistor Array
100%
Fabrication Constraints
100%
Circuit Design
33%
Ultra-low Power
33%
Power Consumption
33%
Area Reduction
33%
Fabrication Methods
33%
Synthetic Approaches
33%
Power Dissipation
33%
State-of-the-art Techniques
33%
Power Source
33%
Leakage Power
33%
Deep Submicron Technology
33%
Design Style
33%
Product Terms
33%
Moore's Law
33%
Automated Synthesis
33%
Dominant Source
33%
Synthesis Algorithm
33%
Electronic Circuit Design
33%
Electronic System Design
33%
Variable Reordering
33%
Engineering
Single Electron
100%
Experimental Result
33%
Low Power Consumption
33%
Energy Dissipation
33%
Circuit Design
33%
Networks (Circuits)
33%
Electric Power Utilization
33%
Early Stage
33%
Area Reduction
33%
Design Style
33%
Moore's Law
33%
State-of-the-Art Technique
33%
Dominant Source
33%
Synthesis Algorithm
33%
Computer Science
Single Electron
100%
Experimental Result
33%
Power Consumption
33%
Moore's Law
33%
low-power consumption
33%
Synthesis Algorithm
33%
Energy Dissipation
33%
Material Science
Transistor
100%
Electronic Circuit
66%