Area minimization synthesis for reconfigurable single-electron transistor arrays with fabrication constraints

Yi Hang Chen*, Jian Yu Chen, Juinn-Dar Huang

*此作品的通信作者

    研究成果: Conference contribution同行評審

    10 引文 斯高帕斯(Scopus)

    摘要

    As fabrication processes exploit even deeper submicron technology, power dissipation has become a crucial issue for most electronic circuit and system designs nowadays. In particular, leakage power is becoming a dominant source of power consumption. Recently, the reconfigurable single-electron transistor (SET) array has been proposed as an emerging circuit design style for continuing Moore's Law due to its ultra-low power consumption. Several automated synthesis approaches have been developed for the reconfigurable SET array in the past few years. Nevertheless, all of those existing methods consider fabrication constraints, which are mandatory, merely in late synthesis stages. In this paper, we propose a synthesis algorithm, featuring both variable reordering and product term reordering, for area minimization. In addition, our algorithm takes those mandatory fabrication constraints into account in early stages for better outcomes. Experimental results show that our new method can achieve an area reduction of up to 24% as compared to current state-of-the-art techniques.

    原文English
    主出版物標題2014 Design, Automation and Test in Europe Conference and Exhibition (DATE)
    發行者Institute of Electrical and Electronics Engineers Inc.
    ISBN(列印)9783981537024
    DOIs
    出版狀態Published - 24 3月 2014
    事件17th Design, Automation and Test in Europe, DATE 2014 - Dresden, Germany
    持續時間: 24 3月 201428 3月 2014

    出版系列

    名字Proceedings -Design, Automation and Test in Europe, DATE
    ISSN(列印)1530-1591

    Conference

    Conference17th Design, Automation and Test in Europe, DATE 2014
    國家/地區Germany
    城市Dresden
    期間24/03/1428/03/14

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