Area-efficient layout design for output transistors with consideration of ESD reliability

Ming-Dou Ker; Chung-Yu Wu; Chien Chang Huang; Hun Hsien Chang; Chau Neng Wu; Ta Lee Yu

doi:10.1109/HKEDM.1996.566324

Area-efficient layout design for output transistors with consideration of ESD reliability

Ming-Dou Ker^*, Chung-Yu Wu, Chien Chang Huang, Hun Hsien Chang, Chau Neng Wu, Ta Lee Yu

^*此作品的通信作者

電子研究所

研究成果: Paper › 同行評審

摘要

A novel hexagon-type layout is proposed to realize large-dimension CMOS output transistors with smaller layout area but higher ESD reliability. The drain parasitic capacitance of hexagon-type layout is also smaller than that of traditional finger-type layout. Experimental results have shown that the maximum driving capability per layout area of output transistor with hexagon-type layout is improved 40% more than that with finger-type layout. This hexagon-type layout is very suitable for deep-submicron low-voltage CMOS IC's in high-density applications.

原文	English
頁面	94-96
頁數	3
DOIs	https://doi.org/10.1109/HKEDM.1996.566324
出版狀態	Published - 1996
事件	Proceedings of the 1996 3rd IEEE Hong Kong Electron Devices Meeting - Hong Kong, Hong Kong 持續時間: 29 6月 1996 → 29 6月 1996

Conference

Conference	Proceedings of the 1996 3rd IEEE Hong Kong Electron Devices Meeting
城市	Hong Kong, Hong Kong
期間	29/06/96 → 29/06/96

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10.1109/HKEDM.1996.566324

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abstract = "A novel hexagon-type layout is proposed to realize large-dimension CMOS output transistors with smaller layout area but higher ESD reliability. The drain parasitic capacitance of hexagon-type layout is also smaller than that of traditional finger-type layout. Experimental results have shown that the maximum driving capability per layout area of output transistor with hexagon-type layout is improved 40% more than that with finger-type layout. This hexagon-type layout is very suitable for deep-submicron low-voltage CMOS IC's in high-density applications.",

author = "Ming-Dou Ker and Chung-Yu Wu and Huang, {Chien Chang} and Chang, {Hun Hsien} and Wu, {Chau Neng} and Yu, {Ta Lee}",

year = "1996",

doi = "10.1109/HKEDM.1996.566324",

language = "English",

pages = "94--96",

note = "Proceedings of the 1996 3rd IEEE Hong Kong Electron Devices Meeting ; Conference date: 29-06-1996 Through 29-06-1996",

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T1 - Area-efficient layout design for output transistors with consideration of ESD reliability

AU - Ker, Ming-Dou

AU - Wu, Chung-Yu

AU - Huang, Chien Chang

AU - Chang, Hun Hsien

AU - Wu, Chau Neng

AU - Yu, Ta Lee

PY - 1996

Y1 - 1996

N2 - A novel hexagon-type layout is proposed to realize large-dimension CMOS output transistors with smaller layout area but higher ESD reliability. The drain parasitic capacitance of hexagon-type layout is also smaller than that of traditional finger-type layout. Experimental results have shown that the maximum driving capability per layout area of output transistor with hexagon-type layout is improved 40% more than that with finger-type layout. This hexagon-type layout is very suitable for deep-submicron low-voltage CMOS IC's in high-density applications.

AB - A novel hexagon-type layout is proposed to realize large-dimension CMOS output transistors with smaller layout area but higher ESD reliability. The drain parasitic capacitance of hexagon-type layout is also smaller than that of traditional finger-type layout. Experimental results have shown that the maximum driving capability per layout area of output transistor with hexagon-type layout is improved 40% more than that with finger-type layout. This hexagon-type layout is very suitable for deep-submicron low-voltage CMOS IC's in high-density applications.

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U2 - 10.1109/HKEDM.1996.566324

DO - 10.1109/HKEDM.1996.566324

M3 - Paper

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SP - 94

EP - 96

T2 - Proceedings of the 1996 3rd IEEE Hong Kong Electron Devices Meeting

Y2 - 29 June 1996 through 29 June 1996

ER -

Area-efficient layout design for output transistors with consideration of ESD reliability

摘要

Conference

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