Area-efficient layout design for output transistors with consideration of ESD reliability

Ming-Dou Ker*, Chung-Yu Wu, Chien Chang Huang, Hun Hsien Chang, Chau Neng Wu, Ta Lee Yu

*此作品的通信作者

研究成果: Paper同行評審

摘要

A novel hexagon-type layout is proposed to realize large-dimension CMOS output transistors with smaller layout area but higher ESD reliability. The drain parasitic capacitance of hexagon-type layout is also smaller than that of traditional finger-type layout. Experimental results have shown that the maximum driving capability per layout area of output transistor with hexagon-type layout is improved 40% more than that with finger-type layout. This hexagon-type layout is very suitable for deep-submicron low-voltage CMOS IC's in high-density applications.

原文English
頁面94-96
頁數3
DOIs
出版狀態Published - 1 12月 1996
事件Proceedings of the 1996 3rd IEEE Hong Kong Electron Devices Meeting - Hong Kong, Hong Kong
持續時間: 29 6月 199629 6月 1996

Conference

ConferenceProceedings of the 1996 3rd IEEE Hong Kong Electron Devices Meeting
城市Hong Kong, Hong Kong
期間29/06/9629/06/96

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