Area-efficient CMOS output buffer with enhanced high ESD reliability for deep submicron CMOS ASIC

Ming-Dou Ker*, Kuo Feng Wang, Mei Chu Joe, Yuan Hua Chu, Tain Shun Wu

*此作品的通信作者

研究成果: Conference article同行評審

12 引文 斯高帕斯(Scopus)

摘要

There are one PTLSCR and one NTLSCR devices in parallel with output PMOS and NMOS devices, respectively, to improve ESD robustness of CMOS output buffer in deep submicron CMOS IC's. PTLSCR (NTLSCR) is merged together with output PMOS (NMOS) device to save layout area for high-density applications. Experimental results show that this proposed CMOS output buffer can sustain up to 4000V (700V) Human-Body-Mode (Machine-Mode) ESD stresses with small layout area in a 0.6-μm CMOS technology with LDD and polycide processes.

原文English
文章編號5218681
頁(從 - 到)123-125
頁數3
期刊Proceedings of the Annual IEEE International ASIC Conference and Exhibit
DOIs
出版狀態Published - 1 12月 1995
事件Proceedings of the 8th Annual IEEE International ASIC Conference and Exhibit - Austin, TX, USA
持續時間: 18 9月 199522 9月 1995

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