TY - JOUR
T1 - Area-efficient CMOS output buffer with enhanced high ESD reliability for deep submicron CMOS ASIC
AU - Ker, Ming-Dou
AU - Wang, Kuo Feng
AU - Joe, Mei Chu
AU - Chu, Yuan Hua
AU - Wu, Tain Shun
PY - 1995/12/1
Y1 - 1995/12/1
N2 - There are one PTLSCR and one NTLSCR devices in parallel with output PMOS and NMOS devices, respectively, to improve ESD robustness of CMOS output buffer in deep submicron CMOS IC's. PTLSCR (NTLSCR) is merged together with output PMOS (NMOS) device to save layout area for high-density applications. Experimental results show that this proposed CMOS output buffer can sustain up to 4000V (700V) Human-Body-Mode (Machine-Mode) ESD stresses with small layout area in a 0.6-μm CMOS technology with LDD and polycide processes.
AB - There are one PTLSCR and one NTLSCR devices in parallel with output PMOS and NMOS devices, respectively, to improve ESD robustness of CMOS output buffer in deep submicron CMOS IC's. PTLSCR (NTLSCR) is merged together with output PMOS (NMOS) device to save layout area for high-density applications. Experimental results show that this proposed CMOS output buffer can sustain up to 4000V (700V) Human-Body-Mode (Machine-Mode) ESD stresses with small layout area in a 0.6-μm CMOS technology with LDD and polycide processes.
UR - http://www.scopus.com/inward/record.url?scp=0029543507&partnerID=8YFLogxK
U2 - 10.1109/ASIC.1995.580696
DO - 10.1109/ASIC.1995.580696
M3 - Conference article
AN - SCOPUS:0029543507
SN - 1063-0988
SP - 123
EP - 125
JO - Proceedings of the Annual IEEE International ASIC Conference and Exhibit
JF - Proceedings of the Annual IEEE International ASIC Conference and Exhibit
M1 - 5218681
T2 - Proceedings of the 8th Annual IEEE International ASIC Conference and Exhibit
Y2 - 18 September 1995 through 22 September 1995
ER -