Architecture exploration and delay minimization synthesis for set-based programmable gate arrays

Keyphrases

• Field Programmable Gate Arrays 100%
• Set-based 100%
• Single Electron Transistor 100%
• Architecture Exploration 100%
• Delay Minimization 100%
• Transistor Array 50%
• Low Power Consumption 25%
• Circuit Design 25%
• Power Consumption 25%
• Room Temperature 25%
• Ultra-low 25%
• Moore's Law 25%
• Synthesis Flow 25%
• Switching Process 25%
• Area-delay Product 25%
• Drivability 25%
• Transistor Network 25%

Computer Science

• Single Electron 100%
• Programmable Gate Array 100%
• Delay Minimization 100%
• Experimental Result 25%
• Power Consumption 25%
• Low Power Consumption 25%
• Moore's Law 25%
• Room Temperature 25%

Engineering

• Single Electron 100%
• Experimental Result 25%
• Low Power Consumption 25%
• Circuit Design 25%
• Electric Power Utilization 25%
• Room Temperature 25%
• Moore's Law 25%