Architecture exploration and delay minimization synthesis for set-based programmable gate arrays

Chia Cheng Wu, Kung Han Ho, Juinn-Dar Huang, Chun Yao Wang

研究成果: Conference contribution同行評審

摘要

Power consumption has become a primary obstacle for circuit designs at present. Single-Electron Transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its low power consumption. Since, only a few electrons are involved in the switching process, the drivability of SETs is ultra-low such that the height of an SET array is limited to a small number. This paper presents a delay minimization synthesis flow that decomposes a circuit into a network of SET Array Blocks (SABs) with a fixed height and width. The experiments were conducted for different sizes of SABs over a set of benchmarks. The experimental results showed that we can have the smallest average Area Delay Product (ADP) when the height is 5 and the width is 10 of an SAB, which indicates that such size of SABs is proper to synthesize SET networks.

原文English
主出版物標題Proceedings - 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018
發行者IEEE Computer Society
頁面257-262
頁數6
ISBN(列印)9781538670996
DOIs
出版狀態Published - 7 8月 2018
事件17th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018 - Hong Kong, Hong Kong
持續時間: 9 7月 201811 7月 2018

出版系列

名字Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
2018-July
ISSN(列印)2159-3469
ISSN(電子)2159-3477

Conference

Conference17th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018
國家/地區Hong Kong
城市Hong Kong
期間9/07/1811/07/18

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