Architecture exploration and delay minimization synthesis for set-based programmable gate arrays

Power consumption has become a primary obstacle for circuit designs at present. Single-Electron Transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its low power consumption. Since, only a few electrons are involved in the switching process, the drivability of SETs is ultra-low such that the height of an SET array is limited to a small number. This paper presents a delay minimization synthesis flow that decomposes a circuit into a network of SET Array Blocks (SABs) with a fixed height and width. The experiments were conducted for different sizes of SABs over a set of benchmarks. The experimental results showed that we can have the smallest average Area Delay Product (ADP) when the height is 5 and the width is 10 of an SAB, which indicates that such size of SABs is proper to synthesize SET networks.