Architectural synthesis frameworks on distributed register-file microarchitecture family

In this work, we first develop a communication synthesis framework targeting the original DRFM. The algorithm aims to optimize both interconnect resources (IIC) and system performance (latency). Then we propose a new distributed register-file based platform-DRFM-IID, where the delay model is one step toward reality. Furthermore, a dedicated synthesis framework for DRFM-IID, which focuses on minimizing the system latency and power consumption simultaneously, is also proposed. We thoroughly investigate all existing woks about distributed register-file microarchitecture family with variant inter-island delay models, and the experimental results indicate that our work does provide better synthesis outcome than the prior art.