Architectural exploration of 3D FPGAs towards a better balance between area and delay

Chia I. Chen*, Bau Cheng Lee, Juinn-Dar Huang

*此作品的通信作者

    研究成果: Conference contribution同行評審

    8 引文 斯高帕斯(Scopus)

    摘要

    The emerging 3D technology, which stacks multiple dies within a single chip and utilizes through-silicon vias (TSVs) as vertical connections, is considered a promising solution for achieving better performance and easy integration. Similarly, a generic 2D FPGA architecture can evolve into a 3D one by extending its signal switching scheme from 2D to 3D by means of TSVs. However, replacing all 2D switch boxes (SBs) by 3D ones with full vertical connectivity is found both area-consuming and resource-squandering. Therefore, it is possible to greatly reduce the footprint with only minor delay increase by properly tailoring the structure and deployment strategy of 3D SB. In this paper, we perform a comprehensive architectural exploration of 3D FPGAs. Various architectural alternatives are proposed and then evaluated thoroughly to pick out the most appropriate ones with a better balance between area and delay. Finally, we recommend several configurations for generic 3D FPGA architectures, which can save up to 52% area with virtually no delay penalty.

    原文English
    主出版物標題Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2011
    頁面587-590
    頁數4
    DOIs
    出版狀態Published - 31 5月 2011
    事件14th Design, Automation and Test in Europe Conference and Exhibition, DATE 2011 - Grenoble, France
    持續時間: 14 3月 201118 3月 2011

    出版系列

    名字Proceedings -Design, Automation and Test in Europe, DATE
    ISSN(列印)1530-1591

    Conference

    Conference14th Design, Automation and Test in Europe Conference and Exhibition, DATE 2011
    國家/地區France
    城市Grenoble
    期間14/03/1118/03/11

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