TY - GEN
T1 - Application of Wafer Defect Pattern Classification Model in the Semiconductor Industry
AU - Lee, Chin Wei
AU - Hládek, Daniel
AU - Pleva, Matúš
AU - Liao, Yuan Fu
AU - Su, Ming Hsiang
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - Deep learning (DL) methods are widely employed in the semiconductor manufacturing process to enhance pattern recognition and classification accuracy, specifically for addressing defect patterns. However, the classification performance of the current models is hindered by the imbalanced distribution of defect data within the test dataset. To tackle this issue, this study presents a feature extraction approach utilizing data transformation, and ensemble learning techniques aiming to enhance the model's classification performance. The primary objective of this study is to mitigate selection and imbalance problems in the dataset through random sampling and assigning distinct weights to individual classifiers. The results demonstrate that the proposed method achieves an impressive accuracy rate of 95.09%, thus substantiating its efficacy in improving the robustness of both the classification model and wafer classification.
AB - Deep learning (DL) methods are widely employed in the semiconductor manufacturing process to enhance pattern recognition and classification accuracy, specifically for addressing defect patterns. However, the classification performance of the current models is hindered by the imbalanced distribution of defect data within the test dataset. To tackle this issue, this study presents a feature extraction approach utilizing data transformation, and ensemble learning techniques aiming to enhance the model's classification performance. The primary objective of this study is to mitigate selection and imbalance problems in the dataset through random sampling and assigning distinct weights to individual classifiers. The results demonstrate that the proposed method achieves an impressive accuracy rate of 95.09%, thus substantiating its efficacy in improving the robustness of both the classification model and wafer classification.
UR - http://www.scopus.com/inward/record.url?scp=85180008836&partnerID=8YFLogxK
U2 - 10.1109/APSIPAASC58517.2023.10317264
DO - 10.1109/APSIPAASC58517.2023.10317264
M3 - Conference contribution
AN - SCOPUS:85180008836
T3 - 2023 Asia Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2023
SP - 2173
EP - 2177
BT - 2023 Asia Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2023
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2023 Asia Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2023
Y2 - 31 October 2023 through 3 November 2023
ER -