Antimony assisted arsenic S/D extension (A3 SDE) engineering for sub-0.1μm nMOSFETs: A novel approach to steep and retrograde indium pocket profiles

Howard C.H. Wang*, C. C. Wang, C. H. Hsieh, S. Y. Lu, M. C. Chiang, Y. L. Chu, C. J. Chen, T. C. Ong, Ta-Hui Wang, Peter B. Griffin, Carlos H. Diaz

*此作品的通信作者

    研究成果: Conference article同行評審

    1 引文 斯高帕斯(Scopus)

    摘要

    We propose a novel process whereby Antimony Assisted Arsenic Source/Drain Extension (A3 SDE) is employed to realize a steep and retrograde indium pocket profile for sub-0.1μm nMOSFETs. By engineering the defect distributions in the amorphous layer created by indium implant, this new process improves 8% current drive while maintaining the same Ioff. It reduces nMOS diode leakage by two orders of magnitude and sidewall junction capacitance near the gate by 14%. Reliability assessment of devices fabricated by the A3 SDE process reveals significant improvement in hot carrier effects and no observable degradation of gate oxide integrity.

    原文English
    頁(從 - 到)63-66
    頁數4
    期刊Technical Digest - International Electron Devices Meeting
    DOIs
    出版狀態Published - 2001
    事件IEEE International Electron Devices Meeting IEDM 2001 - Washington, DC, United States
    持續時間: 2 12月 20015 12月 2001

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