Anomalous substrate current in polycrystalline silicon thin-film transistors

Hsiao-Wen Zan*, Shih Ching Chen, Sheng Hsuan Wang, Chun Yen Chang

*此作品的通信作者

研究成果: Conference contribution同行評審

摘要

In this paper, the substrate current of polycrystalline silicon thin-film transistors was measured and investigated for the first time. With a typical T-gate patterned structure, an abnormally high substrate current was found while devices were operated under high gate voltage. This is generated from the parasitic tunnelling current between the n+ inversion region and the p+ body region. Under lower gate voltage, a substrate current generated from impact ionization effects is also observed and characterized. After extracting fitting parameters from the device characteristics, a simple physically-based model was established and compared with the measured results. A plausible grain boundary scattering effect was included in the proposed model. Good agreement was found through a wide range of gate bias and various drain bias conditions, verifying the validity of this unified model.

原文English
主出版物標題ESSDERC 2003 - Proceedings of the 33rd European Solid-State Device Research Conference
編輯Jose Franca, Paulo Freitas
發行者IEEE Computer Society
頁面469-472
頁數4
ISBN(電子)0780379993
ISBN(列印)9780780379992
DOIs
出版狀態Published - 1 1月 2003
事件33rd European Solid-State Device Research Conference, ESSDERC 2003 - Estoril, Portugal
持續時間: 16 9月 200318 9月 2003

出版系列

名字European Solid-State Device Research Conference
ISSN(列印)1930-8876

Conference

Conference33rd European Solid-State Device Research Conference, ESSDERC 2003
國家/地區Portugal
城市Estoril
期間16/09/0318/09/03

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