Analytical performance models for RLC interconnects and application to clock optimization

Xuejue Huang, Yu Cao, Dennis Sylvester, Tsu Jae King, Chen-Ming Hu

研究成果: Conference contribution同行評審

5 引文 斯高帕斯(Scopus)

摘要

A novel analytical approach for RLC interconnect performance analysis is developed. Using the gate and line geometries as inputs, we derive closed-form expressions for propagation delay, rise time, and voltage overshoot at both the driver output and the far end of the interconnect. This analytical approach enables fast and accurate RLC interconnect analysis and design optimization. Application to clock interconnect optimization is demonstrated and design guidelines are proposed.

原文English
主出版物標題Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
編輯John Chickanosky, Ram K. Krishnamurthy, P.R. Mukund
發行者Institute of Electrical and Electronics Engineers Inc.
頁面353-357
頁數5
ISBN(電子)0780374940
DOIs
出版狀態Published - 1 一月 2002
事件15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 - Rochester, United States
持續時間: 25 九月 200228 九月 2002

出版系列

名字Proceedings of the Annual IEEE International ASIC Conference and Exhibit
2002-January
ISSN(列印)1063-0988

Conference

Conference15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
國家/地區United States
城市Rochester
期間25/09/0228/09/02

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