Analysis of single-trap-induced random telegraph noise on FinFET devices, 6T SRAM cell, and logic circuits

Keyphrases

• FinFET Devices 100%
• Random Telegraph Noise 100%
• Single Trap 100%
• Memory Cell 100%
• Logic Circuit 100%
• Static Random Access Memory 100%
• Cellular Circuits 100%
• Fin Field-effect Transistor (FinFET) 40%
• Charge Trapping 30%
• Noise Degradation 30%
• Independent Gate 20%
• Cell Stability 20%
• Trap Location 10%
• Sidewall 10%
• Multiplexer 10%
• Supply Voltage 10%
• Inverter 10%
• Subthreshold Swing 10%
• Subthreshold 10%
• Bias Dependence 10%
• Conduction Path 10%
• Detrapping 10%
• Mixed-mode Simulation 10%
• 3D TCAD 10%
• TCAD Simulation 10%
• Cell Transistor 10%
• Strong Interaction 10%
• High Temperature Operation 10%
• Current Conduction 10%
• Conduction Characteristics 10%
• Tail Distribution 10%
• Static Noise Margin 10%
• Middle Region 10%
• Noise Amplitude 10%
• Surface Conduction 10%
• Volume Conduction 10%
• EOT Scaling 10%
• Discrete Dopants 10%
• Basic Logic 10%
• VT Shift 10%
• Amplitude Dispersion 10%
• Device Lead 10%

Engineering

• Logic Circuit 100%
• Random Access Memory 100%
• Dopants 33%
• Side Wall 33%
• Supply Voltage 33%
• Mixed Mode 33%
• Noise Margin 33%
• Multiplexer 33%
• High Operating Temperature 33%
• Stability Increase 33%
• Strong Interaction 33%
• Noise Amplitude 33%
• Led Device 33%
• Inverter 33%