Analysis of Negative Capacitance MOSFETs Characteristic with Spacer

Yu Chun Lee; Sekhar Reddy Kola; Chieh Yang Chen; Min Hui Chuang; Yiming Li

doi:10.1109/VLSI-TSA48913.2020.9203692

Analysis of Negative Capacitance MOSFETs Characteristic with Spacer

Yu Chun Lee, Sekhar Reddy Kola, Chieh Yang Chen, Min Hui Chuang, Yiming Li^*

^*此作品的通信作者

電信工程研究所

研究成果: Conference contribution › 同行評審

2 引文斯高帕斯（Scopus）

摘要

In this work, our study comprises of design and investigation on negative capacitance (NC), metal-oxide-semiconductor (MOS) field effects transistors (MOSFETs) with spacer and source/drain (S/D) overlap engineering. The scope of the work is to boost the performance and high-energy efficiency of the studied NC-MOSFETs by using the ferro electric material (FE). The NC-MOSFETs with the spacer technology can achieve the admirable Ion/Ioff ratio and subthreshold swing (SS), compared with planar MOSFETs. It makes device scaling possible by eliminating the short channel effect (SCE). We further estimated the effect of FE thickness and spacer, which are another critical parameter of obtaining better electrical characteristics and reducing SS.

原文	English
主出版物標題	2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020
發行者	Institute of Electrical and Electronics Engineers Inc.
頁面	84-85
頁數	2
ISBN（電子）	9781728142326
DOIs	https://doi.org/10.1109/VLSI-TSA48913.2020.9203692
出版狀態	Published - 8月 2020
事件	2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020 - Hsinchu, Taiwan 持續時間: 10 8月 2020 → 13 8月 2020

出版系列

名字	2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020

Conference

Conference	2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020
國家/地區	Taiwan
城市	Hsinchu
期間	10/08/20 → 13/08/20

UN SDG

此研究成果有助於以下永續發展目標

存取文件

10.1109/VLSI-TSA48913.2020.9203692

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Link to publication in Scopus

引用此

Lee, Y. C., Kola, S. R., Chen, C. Y., Chuang, M. H., & Li, Y. (2020). Analysis of Negative Capacitance MOSFETs Characteristic with Spacer. 於 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020 (頁 84-85). Article 9203692 (2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-TSA48913.2020.9203692

Lee, Yu Chun ; Kola, Sekhar Reddy ; Chen, Chieh Yang 等. / Analysis of Negative Capacitance MOSFETs Characteristic with Spacer. 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020. Institute of Electrical and Electronics Engineers Inc., 2020. 頁 84-85 (2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020).

@inproceedings{078ef000cf3340888745af75dd6f0a35,

title = "Analysis of Negative Capacitance MOSFETs Characteristic with Spacer",

abstract = "In this work, our study comprises of design and investigation on negative capacitance (NC), metal-oxide-semiconductor (MOS) field effects transistors (MOSFETs) with spacer and source/drain (S/D) overlap engineering. The scope of the work is to boost the performance and high-energy efficiency of the studied NC-MOSFETs by using the ferro electric material (FE). The NC-MOSFETs with the spacer technology can achieve the admirable Ion/Ioff ratio and subthreshold swing (SS), compared with planar MOSFETs. It makes device scaling possible by eliminating the short channel effect (SCE). We further estimated the effect of FE thickness and spacer, which are another critical parameter of obtaining better electrical characteristics and reducing SS.",

author = "Lee, {Yu Chun} and Kola, {Sekhar Reddy} and Chen, {Chieh Yang} and Chuang, {Min Hui} and Yiming Li",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020 ; Conference date: 10-08-2020 Through 13-08-2020",

year = "2020",

month = aug,

doi = "10.1109/VLSI-TSA48913.2020.9203692",

language = "English",

series = "2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "84--85",

booktitle = "2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020",

address = "United States",

}

Lee, YC, Kola, SR, Chen, CY, Chuang, MH & Li, Y 2020, Analysis of Negative Capacitance MOSFETs Characteristic with Spacer. 於 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020., 9203692, 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020, Institute of Electrical and Electronics Engineers Inc., 頁 84-85, 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020, Hsinchu, Taiwan, 10/08/20. https://doi.org/10.1109/VLSI-TSA48913.2020.9203692

Analysis of Negative Capacitance MOSFETs Characteristic with Spacer. / Lee, Yu Chun; Kola, Sekhar Reddy; Chen, Chieh Yang 等.
2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020. Institute of Electrical and Electronics Engineers Inc., 2020. p. 84-85 9203692 (2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - Analysis of Negative Capacitance MOSFETs Characteristic with Spacer

AU - Lee, Yu Chun

AU - Kola, Sekhar Reddy

AU - Chen, Chieh Yang

AU - Chuang, Min Hui

AU - Li, Yiming

PY - 2020/8

Y1 - 2020/8

N2 - In this work, our study comprises of design and investigation on negative capacitance (NC), metal-oxide-semiconductor (MOS) field effects transistors (MOSFETs) with spacer and source/drain (S/D) overlap engineering. The scope of the work is to boost the performance and high-energy efficiency of the studied NC-MOSFETs by using the ferro electric material (FE). The NC-MOSFETs with the spacer technology can achieve the admirable Ion/Ioff ratio and subthreshold swing (SS), compared with planar MOSFETs. It makes device scaling possible by eliminating the short channel effect (SCE). We further estimated the effect of FE thickness and spacer, which are another critical parameter of obtaining better electrical characteristics and reducing SS.

AB - In this work, our study comprises of design and investigation on negative capacitance (NC), metal-oxide-semiconductor (MOS) field effects transistors (MOSFETs) with spacer and source/drain (S/D) overlap engineering. The scope of the work is to boost the performance and high-energy efficiency of the studied NC-MOSFETs by using the ferro electric material (FE). The NC-MOSFETs with the spacer technology can achieve the admirable Ion/Ioff ratio and subthreshold swing (SS), compared with planar MOSFETs. It makes device scaling possible by eliminating the short channel effect (SCE). We further estimated the effect of FE thickness and spacer, which are another critical parameter of obtaining better electrical characteristics and reducing SS.

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DO - 10.1109/VLSI-TSA48913.2020.9203692

M3 - Conference contribution

AN - SCOPUS:85093693306

T3 - 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020

SP - 84

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BT - 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020

Y2 - 10 August 2020 through 13 August 2020

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Lee YC, Kola SR, Chen CY, Chuang MH, Li Y. Analysis of Negative Capacitance MOSFETs Characteristic with Spacer. 於 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020. Institute of Electrical and Electronics Engineers Inc. 2020. p. 84-85. 9203692. (2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020). doi: 10.1109/VLSI-TSA48913.2020.9203692

Analysis of Negative Capacitance MOSFETs Characteristic with Spacer

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