Analysis of Latch-Up Holding Voltage for Shallow Trench Cmos

We present an analysis of the latch-up holding voltage of CMOS devices using a lightly doped epitaxially grown layer over a heavily doped substrate, and a well isolation trench of varying depth. Using a simplified simulation scheme it is shown that there exists an optimum epilayer thickness which is somewhat greater than the well depth and leads to maximum holding voltage. Using a relatively shallow trench and with a proper choice of epitaxial layer thickness, the holding voltage can easily be raised above the power supply voltage, thus ensuring freedom from latch-up.