Analysis of Latch-Up Holding Voltage for Shallow Trench Cmos

R. K. Gupta, I. Sakai, Chen-Ming Hu, I. Sakai

研究成果: Article同行評審

1 引文 斯高帕斯(Scopus)

摘要

We present an analysis of the latch-up holding voltage of CMOS devices using a lightly doped epitaxially grown layer over a heavily doped substrate, and a well isolation trench of varying depth. Using a simplified simulation scheme it is shown that there exists an optimum epilayer thickness which is somewhat greater than the well depth and leads to maximum holding voltage. Using a relatively shallow trench and with a proper choice of epitaxial layer thickness, the holding voltage can easily be raised above the power supply voltage, thus ensuring freedom from latch-up.

原文English
頁(從 - 到)1261-1263
頁數3
期刊Electronics Letters
22
發行號23
DOIs
出版狀態Published - 1 1月 1986

指紋

深入研究「Analysis of Latch-Up Holding Voltage for Shallow Trench Cmos」主題。共同形成了獨特的指紋。

引用此