Analysis of an SOC architecture for MPEG reconfigurable video coding framework

Jer Min Hsiao*, Chun-Jen Tsai

*此作品的通信作者

研究成果: Conference article同行評審

13 引文 斯高帕斯(Scopus)

摘要

Due to the variety of popular video coding standards, many efforts have been put into the design of a single video decoder chip that supports multiple formats. In 2004, ISO/IEC MPEG started a new work item to facilitate multi-format video codec design and to enable more flexible usage of coding tools. The work item has turned into the MPEG Reconfigurable Video Coding (RVC) framework. The key concept of the RVC framework is to allow flexible reconfiguration of coding tools to create different codec solutions on-the-fly. In this paper, flexible SoC architecture is proposed to support the RVC framework. Some analysis has been conducted to show the extra costs required for this platform compared to hard-wired codec architecture. In conclusion, the RVC framework can be mapped to an SoC platform to provide flexibility and scalability for dynamic application environment with reasonable cost in hardware design.

原文English
文章編號4252746
頁(從 - 到)761-764
頁數4
期刊Proceedings - IEEE International Symposium on Circuits and Systems
DOIs
出版狀態Published - 2007
事件2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 - New Orleans, LA, United States
持續時間: 27 5月 200730 5月 2007

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