Analysis and mitigation of NBTI-induced performance degradation for power-gated circuits

Keyphrases

• Performance Degradation 100%
• Sleep Transistor 100%
• Circuit Lifetime 66%
• Aging 33%
• Supply Voltage 33%
• Accuracy Analysis 33%
• Proposed Methodology 33%
• Thin Gate Oxide 33%
• PMOS 33%
• Downscaling 33%
• Circuit Performance 33%
• Technology Scaling 33%
• Network Transistor 33%
• Significant Loss 33%
• Reliability Degradation 33%
• Aging Effect 33%
• Scaling Trends 33%
• Active Mode 33%
• Novel Methodology 33%
• Device Aging 33%
• Long-term Performance 33%
• Early Design Phases 33%
• Logic Network 33%
• Aging-aware 33%
• Nanoscale Design 33%
• Optimization Flow 33%
• Reverse Body Bias 33%

Engineering

• Performance Degradation 100%
• Supply Voltage 33%
• Nanoscale 33%
• Gate Oxide 33%
• Logic Circuit 33%
• Circuit Performance 33%
• Main Factor 33%
• Design Stage 33%
• Active Mode 33%
• Aging Effect 33%
• Term Performance 33%