摘要
The high-order Σ-Δ modulator is an appropriate approach for high-bandwidth, high-resolution A/D conversion. However, non-ideal effects such as the finite op-amp gain and the capacitor mismatch have great impacts on its performance at a low oversampling ratio. To achieve greater performance under the inevitable non-ideal effects, we explore several multiple-bit schemes, based on our CIQE high-order Σ-Δ architecture, to remove the non-ideal deterioration. Design rules of these multiple-bit schemes are developed and verified by extensive simulations.
原文 | English |
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頁面 | 419-424 |
頁數 | 6 |
DOIs | |
出版狀態 | Published - 1 1月 1997 |
事件 | Proceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC - Chiba, Jpn 持續時間: 28 1月 1997 → 31 1月 1997 |
Conference
Conference | Proceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC |
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城市 | Chiba, Jpn |
期間 | 28/01/97 → 31/01/97 |