An universal VLSI architecture for bit-parallel computation in GF(2 m)

Chien Ching Lin; Fuh Ke Chang; Hsie-Chia Chang; Chen-Yi Lee

An universal VLSI architecture for bit-parallel computation in GF(2 m)

Chien Ching Lin^*, Fuh Ke Chang, Hsie-Chia Chang, Chen-Yi Lee

^*此作品的通信作者

研究成果: Paper › 同行評審

7 引文斯高帕斯（Scopus）

摘要

In this paper, an universal VLSI architecture for bit-parallel computation in GF(2^m) is presented. The proposed architecture is based on Montgomery multiplication algorithm, which is suitable for multiple class of GF(2^m) with arbitrary field degree m. Due to the highly regular and modular property, our proposed universal architecture can meet VLSI design requirement. After implemented by 0.18um 1P6M process, our universal architecture can work successfully at 125MHz clock rate. For the finite field multiplier, the total gate count is 1.4K for GF(2^m) with any irreducible polynomial of field degree m≤8, whereas the inverse operation can be achieved by the control unit with gate count of 0.3K.¹

原文	English
頁面	125-128
頁數	4
出版狀態	Published - 1 12月 2004
事件	2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan 持續時間: 6 12月 2004 → 9 12月 2004

Conference

Conference	2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
國家/地區	Taiwan
城市	Tainan
期間	6/12/04 → 9/12/04

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abstract = "In this paper, an universal VLSI architecture for bit-parallel computation in GF(2m) is presented. The proposed architecture is based on Montgomery multiplication algorithm, which is suitable for multiple class of GF(2m) with arbitrary field degree m. Due to the highly regular and modular property, our proposed universal architecture can meet VLSI design requirement. After implemented by 0.18um 1P6M process, our universal architecture can work successfully at 125MHz clock rate. For the finite field multiplier, the total gate count is 1.4K for GF(2m) with any irreducible polynomial of field degree m≤8, whereas the inverse operation can be achieved by the control unit with gate count of 0.3K.1",

author = "Lin, {Chien Ching} and Chang, {Fuh Ke} and Hsie-Chia Chang and Chen-Yi Lee",

year = "2004",

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AU - Lin, Chien Ching

AU - Chang, Fuh Ke

AU - Chang, Hsie-Chia

AU - Lee, Chen-Yi

PY - 2004/12/1

Y1 - 2004/12/1

N2 - In this paper, an universal VLSI architecture for bit-parallel computation in GF(2m) is presented. The proposed architecture is based on Montgomery multiplication algorithm, which is suitable for multiple class of GF(2m) with arbitrary field degree m. Due to the highly regular and modular property, our proposed universal architecture can meet VLSI design requirement. After implemented by 0.18um 1P6M process, our universal architecture can work successfully at 125MHz clock rate. For the finite field multiplier, the total gate count is 1.4K for GF(2m) with any irreducible polynomial of field degree m≤8, whereas the inverse operation can be achieved by the control unit with gate count of 0.3K.1

AB - In this paper, an universal VLSI architecture for bit-parallel computation in GF(2m) is presented. The proposed architecture is based on Montgomery multiplication algorithm, which is suitable for multiple class of GF(2m) with arbitrary field degree m. Due to the highly regular and modular property, our proposed universal architecture can meet VLSI design requirement. After implemented by 0.18um 1P6M process, our universal architecture can work successfully at 125MHz clock rate. For the finite field multiplier, the total gate count is 1.4K for GF(2m) with any irreducible polynomial of field degree m≤8, whereas the inverse operation can be achieved by the control unit with gate count of 0.3K.1

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T2 - 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology

Y2 - 6 December 2004 through 9 December 2004

ER -

An universal VLSI architecture for bit-parallel computation in GF(2 m)

摘要

Conference

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