An ultra-low voltage hearing aid chip using variable-latency design technique

Kuo Chiang Chang, Shien Chun Luo, Ching Ji Huang, Chih-Wei Liu, Yuan Hua Chu, Shyh-Jye Jou

    研究成果: Conference contribution同行評審

    1 引文 斯高帕斯(Scopus)

    摘要

    This paper presents a low-power hearing aid chip which operates under near-threshold voltage region to minimize energy consumption. The proposed variable-latency design technique compensates the performance degradation under ultra-low voltage, while the proposed FIR filter computing datapath improves the energy efficiency for filter bank computation in hearing aids. The hearing aid system composed of four heterogeneous processing elements to optimize the flexibility and power consumption. The overall system was fabricated in TSMC 65nm LP process. The measured results show that the power consumption achieves 500 μW at 0.5V and 6 MHz

    原文English
    主出版物標題2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
    發行者Institute of Electrical and Electronics Engineers Inc.
    頁面2543-2546
    頁數4
    ISBN(列印)9781479934324
    DOIs
    出版狀態Published - 2014
    事件2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 - Melbourne, VIC, Australia
    持續時間: 1 6月 20145 6月 2014

    出版系列

    名字Proceedings - IEEE International Symposium on Circuits and Systems
    ISSN(列印)0271-4310

    Conference

    Conference2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
    國家/地區Australia
    城市Melbourne, VIC
    期間1/06/145/06/14

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