An ultra-low voltage hearing aid chip using variable-latency design technique

Kuo Chiang Chang; Shien Chun Luo; Ching Ji Huang; Chih-Wei Liu; Yuan Hua Chu; Shyh-Jye Jou

doi:10.1109/ISCAS.2014.6865691

An ultra-low voltage hearing aid chip using variable-latency design technique

Kuo Chiang Chang, Shien Chun Luo, Ching Ji Huang, Chih-Wei Liu, Yuan Hua Chu, Shyh-Jye Jou

研究成果: Conference contribution › 同行評審

1 引文斯高帕斯（Scopus）

摘要

This paper presents a low-power hearing aid chip which operates under near-threshold voltage region to minimize energy consumption. The proposed variable-latency design technique compensates the performance degradation under ultra-low voltage, while the proposed FIR filter computing datapath improves the energy efficiency for filter bank computation in hearing aids. The hearing aid system composed of four heterogeneous processing elements to optimize the flexibility and power consumption. The overall system was fabricated in TSMC 65nm LP process. The measured results show that the power consumption achieves 500 μW at 0.5V and 6 MHz

原文	English
主出版物標題	2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
發行者	Institute of Electrical and Electronics Engineers Inc.
頁面	2543-2546
頁數	4
ISBN（列印）	9781479934324
DOIs	https://doi.org/10.1109/ISCAS.2014.6865691
出版狀態	Published - 1 1月 2014
事件	2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 - Melbourne, VIC, Australia 持續時間: 1 6月 2014 → 5 6月 2014

出版系列

名字	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN（列印）	0271-4310

Conference

Conference	2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
國家/地區	Australia
城市	Melbourne, VIC
期間	1/06/14 → 5/06/14

UN SDG

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10.1109/ISCAS.2014.6865691

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Link to publication in Scopus

引用此

Chang, K. C., Luo, S. C., Huang, C. J., Liu, C-W., Chu, Y. H., & Jou, S-J. (2014). An ultra-low voltage hearing aid chip using variable-latency design technique. 於 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 (頁 2543-2546). [6865691] (Proceedings - IEEE International Symposium on Circuits and Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2014.6865691

@inproceedings{650b55cae3f8488088fda25b5cdea907,

title = "An ultra-low voltage hearing aid chip using variable-latency design technique",

abstract = "This paper presents a low-power hearing aid chip which operates under near-threshold voltage region to minimize energy consumption. The proposed variable-latency design technique compensates the performance degradation under ultra-low voltage, while the proposed FIR filter computing datapath improves the energy efficiency for filter bank computation in hearing aids. The hearing aid system composed of four heterogeneous processing elements to optimize the flexibility and power consumption. The overall system was fabricated in TSMC 65nm LP process. The measured results show that the power consumption achieves 500 μW at 0.5V and 6 MHz",

author = "Chang, {Kuo Chiang} and Luo, {Shien Chun} and Huang, {Ching Ji} and Chih-Wei Liu and Chu, {Yuan Hua} and Shyh-Jye Jou",

year = "2014",

month = jan,

day = "1",

doi = "10.1109/ISCAS.2014.6865691",

language = "English",

isbn = "9781479934324",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "2543--2546",

booktitle = "2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014",

address = "United States",

note = "2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 ; Conference date: 01-06-2014 Through 05-06-2014",

}

Chang, KC, Luo, SC, Huang, CJ, Liu, C-W, Chu, YH & Jou, S-J 2014, An ultra-low voltage hearing aid chip using variable-latency design technique. 於 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014., 6865691, Proceedings - IEEE International Symposium on Circuits and Systems, Institute of Electrical and Electronics Engineers Inc., 頁 2543-2546, 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014, Melbourne, VIC, Australia, 1/06/14. https://doi.org/10.1109/ISCAS.2014.6865691

An ultra-low voltage hearing aid chip using variable-latency design technique. / Chang, Kuo Chiang; Luo, Shien Chun; Huang, Ching Ji 等.
2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc., 2014. p. 2543-2546 6865691 (Proceedings - IEEE International Symposium on Circuits and Systems).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - An ultra-low voltage hearing aid chip using variable-latency design technique

AU - Chang, Kuo Chiang

AU - Luo, Shien Chun

AU - Huang, Ching Ji

AU - Liu, Chih-Wei

AU - Chu, Yuan Hua

AU - Jou, Shyh-Jye

PY - 2014/1/1

Y1 - 2014/1/1

N2 - This paper presents a low-power hearing aid chip which operates under near-threshold voltage region to minimize energy consumption. The proposed variable-latency design technique compensates the performance degradation under ultra-low voltage, while the proposed FIR filter computing datapath improves the energy efficiency for filter bank computation in hearing aids. The hearing aid system composed of four heterogeneous processing elements to optimize the flexibility and power consumption. The overall system was fabricated in TSMC 65nm LP process. The measured results show that the power consumption achieves 500 μW at 0.5V and 6 MHz

AB - This paper presents a low-power hearing aid chip which operates under near-threshold voltage region to minimize energy consumption. The proposed variable-latency design technique compensates the performance degradation under ultra-low voltage, while the proposed FIR filter computing datapath improves the energy efficiency for filter bank computation in hearing aids. The hearing aid system composed of four heterogeneous processing elements to optimize the flexibility and power consumption. The overall system was fabricated in TSMC 65nm LP process. The measured results show that the power consumption achieves 500 μW at 0.5V and 6 MHz

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U2 - 10.1109/ISCAS.2014.6865691

DO - 10.1109/ISCAS.2014.6865691

M3 - Conference contribution

AN - SCOPUS:84907385735

SN - 9781479934324

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

SP - 2543

EP - 2546

BT - 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014

Y2 - 1 June 2014 through 5 June 2014

ER -

Chang KC, Luo SC, Huang CJ, Liu C-W, Chu YH, Jou S-J. An ultra-low voltage hearing aid chip using variable-latency design technique. 於 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc. 2014. p. 2543-2546. 6865691. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/ISCAS.2014.6865691

An ultra-low voltage hearing aid chip using variable-latency design technique

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