An Ultra-High 6318-PPI Pixel Circuit for Micro-OLED Displays With <inline-formula> <tex-math notation="LaTeX">$V_{\mathrm{th}}$</tex-math> </inline-formula> Compensated up to 10-bit Gray Levels

Shih Song Cheng, Paul C.P. Chao

研究成果: Article同行評審

摘要

An eight FETs and two capacitors (8T2Cs) pixel circuit with dual data voltages (<inline-formula> <tex-math notation="LaTeX">$V_{\text{data}}$</tex-math> </inline-formula>&#x2019;s) is proposed for micro-organic light-emitting diode (OLED) displays, resulting in and validated successfully with an ultra-high pixel-per-inch (PPI) of 6318. This designed pixel circuit can also realize 10-bit threshold voltage (<inline-formula> <tex-math notation="LaTeX">$V_{\text{th}}$</tex-math> </inline-formula>)-compensated gray levels. It is known that conventional displays are 1024 gray levels by inputting 10-bit <inline-formula> <tex-math notation="LaTeX">$V_{\text{data}}$</tex-math> </inline-formula>&#x2019;s to the pixel circuit for generating pixel currents (<inline-formula> <tex-math notation="LaTeX">$I_{\text{pixel}}$</tex-math> </inline-formula>&#x2019;s), resulting in the <inline-formula> <tex-math notation="LaTeX">$V_{\text{data}}$</tex-math> </inline-formula> range of at least 5.12 V with the DAC&#x2019;s 1-LSB of 5 mV assumed. However, for the CMOS processes of dozens of nanometers, only high-voltage FETs (HVFETs) in large sizes can drive with such large <inline-formula> <tex-math notation="LaTeX">$V_{\text{data}}$</tex-math> </inline-formula> range, undermining the chance of high PPI. The new pixel circuit proposes herein low-voltage FETs (LVFETs) in place of most HVFETs successfully by synthesizing two <inline-formula> <tex-math notation="LaTeX">$V_{\text{data}}$</tex-math> </inline-formula>&#x2019;s to generate the required <inline-formula> <tex-math notation="LaTeX">$I_{\text{pixel}}$</tex-math> </inline-formula>&#x2019;s for 10-bit gray levels with the dynamic range of <inline-formula> <tex-math notation="LaTeX">$V_{\text{data}}$</tex-math> </inline-formula> reduced to 0.64 V, while the <inline-formula> <tex-math notation="LaTeX">$V_{\text{th}}$</tex-math> </inline-formula>&#x2019;s can still compensate. This circuit featuring 6318 PPI is successfully fabricated in the chips of the 55-nm CMOS process for validations. The simulation result show that, with <inline-formula> <tex-math notation="LaTeX">$V_{\text{th}}$</tex-math> </inline-formula>&#x2019;s compensated, the <inline-formula> <tex-math notation="LaTeX">$\Delta I_{\mathbf{pixel}}$</tex-math> </inline-formula>&#x2019;s with respect to the currents at corner TT are improved from the averaged <inline-formula> <tex-math notation="LaTeX">$+$</tex-math> </inline-formula>285% of FF to <inline-formula> <tex-math notation="LaTeX">$+$</tex-math> </inline-formula>11.1% and the averaged <inline-formula> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula>69.1% of SS to <inline-formula> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula>9.1%. Favorable voltage linearities were also seen between gray levels. Both DNLs and INLs in the range of <inline-formula> <tex-math notation="LaTeX">$\pm$</tex-math> </inline-formula>1 LSB were measured on a testkey-form circuit, appearing consistency with the simulation results and verifying the expected performance of the designed dual-data-driven pixel circuit.

原文English
頁(從 - 到)1-12
頁數12
期刊IEEE Journal of Solid-State Circuits
DOIs
出版狀態Accepted/In press - 2024

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