An SoC Integration Ready VLIW-Driven CNN Accelerator with High Utilization and Scalability

Chia Heng Hu, I. Hao Tseng, Pei Hsuan Kuo, Juinn Dar Huang

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

In this paper a highly scalable VLIW-driven CNN accelerator architecture is proposed. A new VLIW instruction, which specifies all settings of an entire convolution layer and natively supports layer concatenation, is defined. A multi-mode input aligner (MMIA) is developed to efficiently organize input data for various convolution modes. A zero-initial-latency (ZIL) buffer is created to further boost the performance. A strip-based dataflow is adopted to drastically minimize external DRAM accesses. The accelerator is also equipped with an AXI4 on-chip bus interface, an instruction queue, ping-pong DRAM I/O buffers, and is thus ready for efficient and easy SoC integration. An accelerator instance with 576 MACs has been implemented using TSMC 40nm process. The core logic only requires 490K gates and the total internal memory size is merely 286KB. The peak performance is 1440 GOPS @1.25GHz and the core power efficiency is 8.71 TOPS/W. Moreover, the proposed accelerator has also enabled a real-time image semantic segmentation system for autonomous driving on an FPGA system.

原文English
主出版物標題Proceeding - IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2022
發行者Institute of Electrical and Electronics Engineers Inc.
頁面246-249
頁數4
ISBN(電子)9781665409964
DOIs
出版狀態Published - 2022
事件4th IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2022 - Incheon, Korea, Republic of
持續時間: 13 6月 202215 6月 2022

出版系列

名字Proceeding - IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2022

Conference

Conference4th IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2022
國家/地區Korea, Republic of
城市Incheon
期間13/06/2215/06/22

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