An RRAM-Based 40.6 TOPS/W Energy-Efficient AI Inference Accelerator with Quad Neuromorphic-Processor-Unit for Highly Contrast Recognition

Y. L. Lin, Y. R. Liu, T. C. Kao, M. Y. Lee, J. C. Guo, T. H. Hou, Steve S. Chung

研究成果: Conference contribution同行評審

摘要

We present a non-volatile edge deep neural network accelerator with a resistive-gate FinFET (RG-FinFET) memory and a parallel processor for edge AI inference. The RG-FinFET has the potential for 8-level operation. In the system, data storage and multiplication are carried out in the RG-FinFET array, and all the other operations are performed in a 4-core neuromorphic processing units (NPU). Quantization error is introduced into training stage through ex-Situ quantized training method, thus, the accuracy can still reach 97.24% and 80.18% respectively for MNIST and CIFAR-10 datasets while the parameter capacity is nearly 8x smaller. Eventually, the system's computation efficiency with 40.6 TOPS/w can be achieved, which is well-suited for the end-to-end integer-only AI-Inference hardware in CIM.

原文English
主出版物標題2024 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2024 - Proceedings
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9798350360349
DOIs
出版狀態Published - 2024
事件2024 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2024 - Hsinchu, 台灣
持續時間: 22 4月 202425 4月 2024

出版系列

名字2024 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2024 - Proceedings

Conference

Conference2024 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2024
國家/地區台灣
城市Hsinchu
期間22/04/2425/04/24

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