An MPEG-4 shape-adaptive inverse DCT with zero skipping and auto-aligned transpose memory

Hui Cheng Hsu*, Kun B. Lee, N. Y C Chang, Tian-Sheuan Chang

*此作品的通信作者

    研究成果: Paper同行評審

    2 引文 斯高帕斯(Scopus)

    摘要

    This paper presents an efficient VLSI architecture of shape-adaptive inverse discrete cosine transform (SA-IDCT) for the MPEG-4 video system. The proposed architecture contains a cost-effective 1-D variable-length IDCT engine and an auto-aligned transpose memory organization. The proposed design exploits the properties of SA-IDCT transform matrix to reduce area and improve throughput. Besides, the auto-aligned transpose memory organization can achieve transposing, shifting and aligning simultaneously with the capability of zero skipping. Compared to other designs, our architecture has higher throughout and lower power dissipation. When clocking at 62.5 MHz, the proposed architecture has a throughput of 401.41Mpixels/sec and power dissipation of 5.56 mW/sample @ 1.8V, 62.5MHz.

    原文English
    頁面773-776
    頁數4
    DOIs
    出版狀態Published - 12月 2004
    事件2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan
    持續時間: 6 12月 20049 12月 2004

    Conference

    Conference2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
    國家/地區Taiwan
    城市Tainan
    期間6/12/049/12/04

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