An LDPC decoder chip based on self-routing network for IEEE 802.16e applications

Chih Hao Liu*, Shau Wei Yen, Chih Lung Chen, Hsie-Chia Chang, Chen-Yi Lee, Yar Sun Hsu, Shyh-Jye Jou

*此作品的通信作者

    研究成果: Article同行評審

    107 引文 斯高帕斯(Scopus)

    摘要

    An LDPC decoder chip fully compliant to IEEE 802.16e applications is presented. Since the parity check matrix can be decomposed into sub-matrices which are either a zero-matrix or a cyclic shifted matrix, a phase-overlapping message passing scheme is applied to update messages immediately, leading to enhance decoding throughput. With only one shifter-based permutation structure, a self-routing switch network is proposed to merge 19 different sub-matrix sizes as defined in IEEE 802.16e and enable parallel message to be routed without congestion. Fabricated in the 90 nm 1P9M CMOS process, this chip achieves 105 Mb/s at 20 iterations while decoding the rate-5/6 2304-bit code at 150 MHz operation frequency. To meet the maximum data rate in IEEE 802.16e, this chip operates at 109 MHz frequency and dissipates 186 mW at 1.0 V supply.

    原文English
    文章編號4456784
    頁(從 - 到)684-694
    頁數11
    期刊IEEE Journal of Solid-State Circuits
    43
    發行號3
    DOIs
    出版狀態Published - 1 3月 2008

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