An inverter based 2-MHz 42-μW △Σ ADC with 20-KHz bandwidth and 66dB dynamic range

Chau-Chin Su; Po Chen Lin; Hung Wen Lu

doi:10.1109/ASSCC.2006.357852

An inverter based 2-MHz 42-μW △Σ ADC with 20-KHz bandwidth and 66dB dynamic range

Chau-Chin Su^*, Po Chen Lin, Hung Wen Lu

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電機工程學系

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10 引文斯高帕斯（Scopus）

摘要

This paper presented an inverter based 3^rdorder sigma-delta ADC. Cascode structure and auto-zeroing mechanism are proposed for the gain enhancement and offset cancel-lation. The ADC has been implemented in TSMC 2P6M 0.18μm CMOS technology with a core area of 0.54mm² The measurement results show that for the 1-V supply, 20-KHz bandwidth, and 2-MHz sampling rate, the power consumption is 42μW and the dynamic range of 66.02dB.

原文	English
頁面	63-66
頁數	4
DOIs	https://doi.org/10.1109/ASSCC.2006.357852
出版狀態	Published - 1 12月 2006
事件	2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 - Hangzhou, 中國持續時間: 13 11月 2006 → 15 11月 2006

Conference

Conference	2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006
國家/地區	中國
城市	Hangzhou
期間	13/11/06 → 15/11/06

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10.1109/ASSCC.2006.357852

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title = "An inverter based 2-MHz 42-μW △Σ ADC with 20-KHz bandwidth and 66dB dynamic range",

abstract = "This paper presented an inverter based 3rdorder sigma-delta ADC. Cascode structure and auto-zeroing mechanism are proposed for the gain enhancement and offset cancel-lation. The ADC has been implemented in TSMC 2P6M 0.18μm CMOS technology with a core area of 0.54mm2 The measurement results show that for the 1-V supply, 20-KHz bandwidth, and 2-MHz sampling rate, the power consumption is 42μW and the dynamic range of 66.02dB.",

author = "Chau-Chin Su and Lin, {Po Chen} and Lu, {Hung Wen}",

year = "2006",

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doi = "10.1109/ASSCC.2006.357852",

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Y1 - 2006/12/1

N2 - This paper presented an inverter based 3rdorder sigma-delta ADC. Cascode structure and auto-zeroing mechanism are proposed for the gain enhancement and offset cancel-lation. The ADC has been implemented in TSMC 2P6M 0.18μm CMOS technology with a core area of 0.54mm2 The measurement results show that for the 1-V supply, 20-KHz bandwidth, and 2-MHz sampling rate, the power consumption is 42μW and the dynamic range of 66.02dB.

AB - This paper presented an inverter based 3rdorder sigma-delta ADC. Cascode structure and auto-zeroing mechanism are proposed for the gain enhancement and offset cancel-lation. The ADC has been implemented in TSMC 2P6M 0.18μm CMOS technology with a core area of 0.54mm2 The measurement results show that for the 1-V supply, 20-KHz bandwidth, and 2-MHz sampling rate, the power consumption is 42μW and the dynamic range of 66.02dB.

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T2 - 2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006

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An inverter based 2-MHz 42-μW △Σ ADC with 20-KHz bandwidth and 66dB dynamic range

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