An integrated placement and routing for ratioed capacitor array based on ILP formulation

Pang Yen Chou, Po-Hung Lin, Helmut Graeb

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

Capacitor arrays are widely used in analog and mixed-signal circuit design. Most previous works solve the placement and routing problem either in a two-stage fashion or iteratively in loops, which may be more time-consuming or have less routing consideration in the placement step. To our best knowledge, this work is the first to formulate capacitor array placement and routing problem together and solve at once. Experimental results show that the proposed approach requires shorter time to reach comparable results to previous work. The formulation also provides possibilities for adding more placement and routing constraints in the future if they can fit into the Integer Linear Programming (ILP) form.

原文English
主出版物標題2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781467394987
DOIs
出版狀態Published - 31 五月 2016
事件2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 - Hsinchu, Taiwan
持續時間: 25 四月 201627 四月 2016

出版系列

名字2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

Conference

Conference2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
國家/地區Taiwan
城市Hsinchu
期間25/04/1627/04/16

指紋

深入研究「An integrated placement and routing for ratioed capacitor array based on ILP formulation」主題。共同形成了獨特的指紋。

引用此