TY - GEN
T1 - An integrated 60-GHz front-end receiver with a frequency tripler using 0.13-um CMOS technology
AU - Chen, Po-Hung
AU - Chen, Min Chiao
AU - Wu, Chung-Yu
PY - 2007/12/1
Y1 - 2007/12/1
N2 - In this paper, a 60-GHz CMOS direct-conversion receiver integrated with a frequency tripler is proposed. The proposed receiver consists of a low-noise amplifier (LNA), a down-conversion mixer, output buffers, and a frequency tripler. This chip is designed using 0.13-um CMOS technology. By using a frequency tripler, the operating frequency of the PLL can be reduced from 60 GHz to 20 GHz. This makes the implementation of the PLL much easier. According to the simulation results, the receiver has a noise figure (NF) of 7.6 dB, a power gain of 29.2 dB. It consumes 14.2 mW from a 1.2-V power supply.
AB - In this paper, a 60-GHz CMOS direct-conversion receiver integrated with a frequency tripler is proposed. The proposed receiver consists of a low-noise amplifier (LNA), a down-conversion mixer, output buffers, and a frequency tripler. This chip is designed using 0.13-um CMOS technology. By using a frequency tripler, the operating frequency of the PLL can be reduced from 60 GHz to 20 GHz. This makes the implementation of the PLL much easier. According to the simulation results, the receiver has a noise figure (NF) of 7.6 dB, a power gain of 29.2 dB. It consumes 14.2 mW from a 1.2-V power supply.
UR - http://www.scopus.com/inward/record.url?scp=50649089787&partnerID=8YFLogxK
U2 - 10.1109/ICECS.2007.4511119
DO - 10.1109/ICECS.2007.4511119
M3 - Conference contribution
AN - SCOPUS:50649089787
SN - 1424413788
SN - 9781424413782
T3 - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
SP - 829
EP - 832
BT - ICECS 2007 - 14th IEEE International Conference on Electronics, Circuits and Systems
Y2 - 11 December 2007 through 14 December 2007
ER -