TY - GEN
T1 - An incremental analog-to-digital converter with multi-step extended counting for sensor interfaces
AU - Chen, Chia-Hung
AU - Zhang, Yi
AU - He, Tao
AU - Temes, Gabor C.
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/7/29
Y1 - 2016/7/29
N2 - Integrated sensor interface circuits require power-efficient high-accuracy data converters. In many applications, the best choice is the incremental A/D converters (IADCs) incorporating extended counting. In this paper, we discuss the operation and design of single- and multi-stage IADCs. By using a direct-input feed-forward modulator, the IADC accumulates the residue voltage, and it is easy to implement a hybrid scheme of extended counting. Several hybrid schemes are reviewed and discussed. The energy efficiency c an be improved significantly by re-using the hardware to perform extended counting. A multi-step extended counting scheme is proposed for high-resolution power-efficient conversion. A design example with OSR=320 is described in this paper. By using multi-step extended counting, the SQNR performance is boosted to 108 dB, which is much better than that of a second-order IADC of the same OSR, 94 dB.
AB - Integrated sensor interface circuits require power-efficient high-accuracy data converters. In many applications, the best choice is the incremental A/D converters (IADCs) incorporating extended counting. In this paper, we discuss the operation and design of single- and multi-stage IADCs. By using a direct-input feed-forward modulator, the IADC accumulates the residue voltage, and it is easy to implement a hybrid scheme of extended counting. Several hybrid schemes are reviewed and discussed. The energy efficiency c an be improved significantly by re-using the hardware to perform extended counting. A multi-step extended counting scheme is proposed for high-resolution power-efficient conversion. A design example with OSR=320 is described in this paper. By using multi-step extended counting, the SQNR performance is boosted to 108 dB, which is much better than that of a second-order IADC of the same OSR, 94 dB.
KW - analog-to-digital converter (ADC)
KW - delta sigma (ΔΣ)
KW - extended-counting
KW - incremental data converters
KW - measurement and instrumentation
KW - multi-stage noise shaping (MASH)
KW - multi-step
KW - sensor interface
KW - time-domain analysis
KW - two step
UR - http://www.scopus.com/inward/record.url?scp=84983452551&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2016.7527174
DO - 10.1109/ISCAS.2016.7527174
M3 - Conference contribution
AN - SCOPUS:84983452551
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 77
EP - 80
BT - ISCAS 2016 - IEEE International Symposium on Circuits and Systems
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016
Y2 - 22 May 2016 through 25 May 2016
ER -
