An hardware efficient deblocking filter for H.264/AVC

Chao Chung Cheng*, Tian-Sheuan Chang

*此作品的通信作者

    研究成果: Conference article同行評審

    31 引文 斯高帕斯(Scopus)

    摘要

    This paper presents an efficient VLSI architecture for the deblocking filter in H.264/AVC standard. The computing flow is reordered for easy hardware implementation. The resulting design can achieve 100 MHz with only gate count of 9.16K when synthesized from verilog RTL design by using UMC 0.18μm CMOS technology. When clocked at 82.58MHz, our design can easily support real-tune deblocking of 2K×1K@30Hz video application, this high performance can meet high resolution real-time application requirement

    原文English
    文章編號6.4-1
    頁(從 - 到)235-236
    頁數2
    期刊Digest of Technical Papers - IEEE International Conference on Consumer Electronics
    DOIs
    出版狀態Published - 2005
    事件2005 Digest of Technical Papers - International Conference on Consumer Electronics, ICCE 2005 - Las Vegas, NV, United States
    持續時間: 8 1月 200512 1月 2005

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