TY - JOUR
T1 - An hardware efficient deblocking filter for H.264/AVC
AU - Cheng, Chao Chung
AU - Chang, Tian-Sheuan
PY - 2005
Y1 - 2005
N2 - This paper presents an efficient VLSI architecture for the deblocking filter in H.264/AVC standard. The computing flow is reordered for easy hardware implementation. The resulting design can achieve 100 MHz with only gate count of 9.16K when synthesized from verilog RTL design by using UMC 0.18μm CMOS technology. When clocked at 82.58MHz, our design can easily support real-tune deblocking of 2K×1K@30Hz video application, this high performance can meet high resolution real-time application requirement
AB - This paper presents an efficient VLSI architecture for the deblocking filter in H.264/AVC standard. The computing flow is reordered for easy hardware implementation. The resulting design can achieve 100 MHz with only gate count of 9.16K when synthesized from verilog RTL design by using UMC 0.18μm CMOS technology. When clocked at 82.58MHz, our design can easily support real-tune deblocking of 2K×1K@30Hz video application, this high performance can meet high resolution real-time application requirement
UR - http://www.scopus.com/inward/record.url?scp=28044450124&partnerID=8YFLogxK
U2 - 10.1109/ICCE.2005.1429804
DO - 10.1109/ICCE.2005.1429804
M3 - Conference article
AN - SCOPUS:28044450124
SN - 0747-668X
SP - 235
EP - 236
JO - Digest of Technical Papers - IEEE International Conference on Consumer Electronics
JF - Digest of Technical Papers - IEEE International Conference on Consumer Electronics
M1 - 6.4-1
T2 - 2005 Digest of Technical Papers - International Conference on Consumer Electronics, ICCE 2005
Y2 - 8 January 2005 through 12 January 2005
ER -